I2S slave lost syncronization

[heifetsg]

Posted on September 03, 2017 at 08:50

Hello,

I use I2S interface on STM32F446 to read audio stream in slave mode. The master transmits MCLK, BCLK, DATA and WS signals.

At the beginning everything works fine. At random point in time the stream becomes disrupted.

I suspect that maybe noise on the I2S line causes that.

What synchronizes data reception alignment? Is it done at WS rise/fall, only first time or every cycle?

What happens if the I2S module receives additional clock due to noise? Will it recover? Is there an error flag?

Best regards,

Gregory

https://my.st.com/tmtrack/images/t1x1.gif

https://my.st.com/tmtrack/images/t1x1.gif

stm32 audio i2s

[waclawek.jan]

Posted on September 03, 2017 at 12:22

Good question.

How do you set SPI_I2SCFGR.ASTREN?

JW

PS. In Cube, SPL and errata this bit is spelled as ASTRTEN...

[ESuba.3]

Any solution?,