I cannot see the status of the registers DFSDM1_Filter2 and DFSDM1_Filter3 in register view STM32l496ZG.

[Dumpler]

When you configure DFSDM faced with the problem that I can't see the status registers a custom filter, due to incorrect file STM32L4x6.svd because the register addresses according to this file do not match those described in the Datasheet and in the HAL library.

On the site of ST not submitted file STM32L4x6.svd which would have been valid addresses.

Does it exist and where can I get it?

Datasheet DocID029173 Rev 7

0x4001 6000 - 0x4001 63FF DFSDM1

stm32l496xx.h

#define PERIPH_BASE       ((uint32_t)0x40000000U)

#define APB2PERIPH_BASE     (PERIPH_BASE + 0x00010000U)

#define DFSDM1_BASE      (APB2PERIPH_BASE + 0x6000U)

#define DFSDM1_Filter0_BASE  (DFSDM1_BASE + 0x100)

#define DFSDM1_Filter1_BASE  (DFSDM1_BASE + 0x180)

#define DFSDM1_Filter2_BASE  (DFSDM1_BASE + 0x200)

#define DFSDM1_Filter3_BASE  (DFSDM1_BASE + 0x280)

STM32L4x6.svd

<name>DFSDM0_CR1</name>

<displayName>DFSDM0_CR1</displayName>

<description>control register 1</description>

<addressOffset>0x100</addressOffset>

<name>DFSDM1_CR1</name>

<displayName>DFSDM1_CR1</displayName>

<description>control register 1</description>

<addressOffset>0x200</addressOffset>

<name>DFSDM2_CR1</name>

<displayName>DFSDM2_CR1</displayName>

<description>control register 1</description>

<addressOffset>0x300</addressOffset>

<name>DFSDM3_CR1</name>

<displayName>DFSDM3_CR1</displayName>

<description>control register 1</description>

<addressOffset>0x400</addressOffset>

[Imen.D]

Hello @Dumpler​ ,

Do you mean svd file missing DFSDM1_FLT2 and DFSDM1_FLT3 ?

I checked the version STM32L4_svd_V1.2 and found these  global interrupt.

Kind Regards,

Imen

[Dumpler]

This interrupt, in order to see the register values I had to modify the svd file according to the values from HAL, only then everything worked as it should.

<name>DFSDM0_CR1</name>

<displayName>DFSDM0_CR1</displayName>

<description>control register 1</description>

<addressOffset>0x100</addressOffset>

<name>DFSDM0_CR2</name>

<displayName>DFSDM1_CR2</displayName>

<description>control register 2</description>

<addressOffset>0x104</addressOffset>

<name>DFSDM1_CR1</name>

<displayName>DFSDM1_CR1</displayName>

<description>control register 1</description>

<addressOffset>0x180</addressOffset>

<name>DFSDM1_CR2</name>

<displayName>DFSDM1_CR2</displayName>

<description>control register 2</description>

<addressOffset>0x184</addressOffset>

<name>DFSDM2_CR1</name>

<displayName>DFSDM2_CR1</displayName>

<description>control register 1</description>

<addressOffset>0x200</addressOffset>

<name>DFSDM2_CR2</name>

<displayName>DFSDM2_CR2</displayName>

<description>control register 2</description>

<addressOffset>0x204</addressOffset>

<name>DFSDM3_CR1</name>

<displayName>DFSDM3_CR1</displayName>

<description>control register 1</description>

<addressOffset>0x280</addressOffset>

<name>DFSDM3_CR2</name>

<displayName>DFSDM3_CR2</displayName>

<description>control register 2</description>

<addressOffset>0x284</addressOffset>

and other addresses.

[Imen.D]

Thanks for your contirbution to improve our products.

This issue is confirmed and the fix will be published soon in the next release.

Best Regards,

Imen