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mur
Associate III
Apr 13, 2020 3:20 PM UTC
Solved

DMA and UART not triggering completion INT sometimes

Hi,

I'm using serial communication with DMA and sometimes the transmission complete interrupt is not triggered (HAL_UART_TxCpltCallback) the issue happens every few minutes, or every several hundred transmissions.

I saw https://community.st.com/s/question/0D50X00009XkfArSAJ/dmausart-on-stm32f407vg-tc-interrupt-sometimes-not-triggered and I think it may be related: I am putting variable length messages into the DMA and I wonder whether there's constraints in the length that can be set.

I have tested for some time now triying to find a pattern and in all cases the data packet length was pretty small, whenever the DMA stopped triggering the interrupt, the lengths were 17, 11, 5, 5, 3, 5 (6 different tests).

So the questoin is, is there any limitation in the data length to set into the DMA?

For sending, I'm using HAL's HAL_UART_Transmit_DMA()

Best regards.

This topic has been closed for replies.
waclawek.jan
waclawek.janBest answer
Super User
Apr 13, 2020 9:26 PM UTC

The 'F3's DMA does not have FIFO.

There's no particular length limitation for USART/DMA. I believe it's coincidental that you see problems with odd lengths.

JW

5 replies

waclawek.jan
Super User
Apr 13, 2020 4:58 PM UTC

The issue in the linked thread is related to FIFO. Do you use FIFO in DMA? Read out and post the DMA registers' content in case of problematic length.

JW

mur
murAuthor
Associate III
Apr 13, 2020 7:47 PM UTC

I don't know, I'm using the automatic configuration from stm32cubeIDE. I know I'm using the DMA in Normal mode with an increment size of a byte.

I tried browsing for FIFO in the reference manual of my device (stm32f334r8, RM0364) and FIFO was only mentioned along DMA in the SPI section. Is it the same FIFO?

waclawek.jan
waclawek.janBest answer
Super User
Apr 13, 2020 9:26 PM UTC

The 'F3's DMA does not have FIFO.

There's no particular length limitation for USART/DMA. I believe it's coincidental that you see problems with odd lengths.

JW

mur
murAuthor
Associate III
Apr 14, 2020 2:57 PM UTC

Indeed, the interrupt was not triggered because the transfer was not started. The source was a race condition in my code. Thanks for your time.

BR.

waclawek.jan
Super User
Apr 14, 2020 7:11 PM UTC

Thanks for coming back with the solution.

JW