D cache blocks whole running program on Nucleo h7s3l8 (even if MPU configured)

[s319189]

As the title suggests My program on a Nucleo H7S3L8 stops running when D cache is enabled (appearently it does not go into Hardfault mode). However, when the line SCB_EnableDCache() is commented, it starts again running. Since I need D cache I configured the MPU for where the dma buffers of the project are located, since I’ve read that it could be a cache coherency problem with DMAs, but neither this solution solves the problem. I’ve read somewhere that is XSPI2_HSLV OTP that must be enabled on STM32CubeProgrammer, but I’ve checked and this is enabled! How the problem can be solved? I’ll upload the project

[Pavel A.]

In your .ld file the appli XSPI memory is mapped at 0x70000000.

But in your MPU_Config (main.c) there’s no definition for this address range, and the whole function is just buggy and does not do what intended. Please review it.

 

[s319189]

I’ve created a new project without touching the standard configuration for MPU and I admit you were right, now the yello led blinking means that program is running. However, I2S peripherals still have cache coherency problem even if using SCB_InvalidateDCache and SCB_CleanDCache() instead of MPU config. I don’t what is a concrete working solution that solves even Cache coherency problem of I2S peripherals

[Saket_Om]

Hello ​@s319189 

If you want to keep the I2S DMA buffer region cacheable for performance, you must strictly respect the cache line constraints below:

• Each I2S DMA buffer must start at a 32‑byte aligned address.
• Each buffer size must be a multiple of 32 bytes.