Communication of LAN9253 with STM32F446ZCH6 using Quad SPI

[DDS]

I am trying to establish communication between an STM32F446ZCH6 and a LAN9253 using the Quad SPI (QSPI) interface on our custom hardware.

As an initial validation, I am attempting to read the following LAN9253 registers:

• BYTE_TEST register (0x64)

• ID_REV (Chip ID) register (0x50)

However, I am not receive the expected register values. Instead, the values returned are consistently 0x88888888 or 0xFFFFFFFF.

To troubleshoot the issue, I captured the SPI/QSPI communication using a logic analyzer. From the waveforms, it appears that:

• The STM32 (master) is transmitting the read command correctly.

• The clock (SCK) and chip select (CS) signals appear normal.

• However, the LAN9253 does not respond with valid data, and the STM32 does not receive any meaningful data from the slave.

We also attempted communication using:

• Single SPI (1-bit mode)

• Dual SPI (2-bit mode)

• Quad SPI (4-bit mode)

Unfortunately, the behavior is the same in all three modes, with no valid response from the LAN9253.

We have verified the hardware and found the following:

• LAN9253 supply voltage: 3.3 V (stable)

• RESET pin: High (device is out of reset)

• Crystal oscillator: 25 MHz, confirmed on the oscilloscope

One additional observation from the logic analyzer is that:

• IO3 remains pulled high throughout the communication.

• IO0, IO1, and IO2 remain low, and no response is observed from the slave device.

This is a custom board containing the STM32F446ZCH6 and LAN9253.

I will attach:

• Logic analyzer waveform screenshots

• Relevant source code used for the register read operation

Has anyone encountered a similar issue with the LAN9253? Are there any additional hardware checks, initialization steps, bootstrap requirements, or QSPI/SPI timing considerations that I should verify? Any suggestions would be greatly appreciated.