Best way to handle SDRAM + LTDC together on STM32H7 without cache artifacts?

[james4452]

I'm working on an STM32H743-based project driving a parallel LCD through LTDC, with the framebuffer sitting in external SDRAM via FMC. I keep running into intermittent display corruption that I suspect is cache-related, since the M7 core has D-Cache enabled by default.

What's the recommended approach for setting up the MPU region for the framebuffer — mark the whole SDRAM region as non-cacheable, or is it better to keep caching enabled and handle cache maintenance manually (SCB_CleanDCache_by_Addr) around framebuffer writes? Curious what's worked best for people running LTDC + SDRAM at higher resolutions/refresh rates without a performance hit.

[MM..1]

Start with Introduction to LCD-TFT display controller (LTDC) for STM32 MCUs - Application note

[mƎALLEm]

Hello,

AN4861 “Introduction to LCD-TFT display controller (LTDC) for STM32 MCUs” / especially the section 5.6 Special recommendations for Cortex M7 (STM32F7/H7) and Cortex M55 (STM32N6).

1- Need to ensure to prevent any CM7 speculative access to an invalid address region to prevent any loss of display performance. Read also this article:

2- Ensure the data coherency. Read “MPU and cache policy configuration” section in the same AN4861

Hope that helps.