SWO also on CS of a SPI EEPROM is safe/state of the art?

[_richard]

i got schematics for a board that i should work on. it's stm32 L0 based.

they did put SWO also on CS of a SPI EEPROM. I'm not a hardware designer / debug protocol specialist but i could imagine debug scenarios where toggling the chip select of an EEPROM while debugging leads to unexpected results.

Would you say that putting SWO also on CS of a SPI EEPROM is safe / state of the art?

[Peter BENSCH]

Which STM32L0 do you have that has a SWO output?

Regards

/Peter

[Pavel A.]

These days... they call art a rotten banana stuck on a wall. Who knows.

[_richard]

that's a good question.

they did label pb3 at the stm32l072 as SWO, as well as the pin 6 at tag connect, and then they have pb3 also labelled as cs_ee at another sheet.

after your question i looked into the l072 manual and found that it has no SWO -> the labeling is wrong.

well, I'm not a hardware designer and try to work based on the info i get

[Peter BENSCH]

No problem - everyone stumbles across a misleading term or other inconsistency once in a while.

If the problem is solved, please mark this thread as answered by selecting Select as best, as also explained here. This will help other users find that answer faster.

Good luck!

/Peter