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Associate II
January 15, 2025
Question

STM32G0B1RE output clock

Hello everyone and thank you for taking the time to read my post.

 

The problem I'm encountering is regarding the configuration of MCO.

I configured MCOSEL and MCOPRE to use PLLRCLK with a 1 prescaler value. The PLLR clock is configured with a frequency of 64 MHz.

I also activated GPIOAEN in RCC registers and configured PA8 for alternate function 0, push&pull, no push, no pull, low speed and i dont get the clock at all. If i connect an oscilloscope to a pin direclty touching SB17 on the board, i can see the rectangular signal and its generated well, but when I try using PA8 it doesn't work. I have connected a GND referencec to the oscilloscope as well.

For reference, I will leave here the snippet of code:

 

static void MX_GPIO_Init(void)
{
 GPIO_InitTypeDef GPIO_InitStruct = {0};
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */

 /* GPIO Ports Clock Enable */
 __HAL_RCC_GPIOA_CLK_ENABLE();

 /*Configure GPIO pin : PA8 */
 GPIO_InitStruct.Pin = GPIO_PIN_8;
 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 GPIO_InitStruct.Pull = GPIO_NOPULL;
 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);

/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}

 

This topic has been closed for replies.

5 replies

Andrew Neil
Super User
January 15, 2025

@undacmic wrote:

low speed


Try high?

A complex system that works is invariably found to have evolved from a simple system that worked.A complex system designed from scratch never works and cannot be patched up to make it work.
undacmicAuthor
Associate II
January 16, 2025

I tried different combinations, it seems like HIGH and VERY HIGH speed are the ones that output my clock.

Mike_ST
ST Technical Moderator
January 15, 2025

Hello,

- SB17 is connected the MCO coming from the ST-Link V2, this 8MHz clock can be used as input clock for the STM32G0 when SB17 is closed.
it has almost nothing to do with MCO of the STM32G0.

- If you're using the HAL library, you can call the
HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) function. In theory, it configures the registers automatically.
Example: HAL_RCC_MCOConfig(RCC_MCO_PA8, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);

- Check you are probing the right pins:
PA8 is on CN9/PIN8 or CN10/PIN23

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undacmicAuthor
Associate II
January 16, 2025

@Mike_ST wrote:

- SB17 is connected the MCO coming from the ST-Link V2, this 8MHz clock can be used as input clock for the STM32G0 when SB17 is closed.
it has almost nothing to do with MCO of the STM32G0.


Oh, I was not aware of this, this really misguided me as I was basing my measurements on this. Thank you.

 


@Mike_ST wrote:

- If you're using the HAL library, you can call the
HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) function.


I am just using HAL library for benchmarking what I do in my own setup which looks something like this:

 

static const io_config io_default_configs[IO_PORT_CNT * IO_PIN_CNT] = {
 [0 ... (IO_PORT_CNT * IO_PIN_CNT -1)] = { IO_ANALOG, 0, 0, 0, 0, 0 },
 [IO_USART2_TX] = { IO_ALTERNATE_FUNCTION, IO_AF1, IO_PUSH_PULL, IO_VERY_HIGH_S, IO_NONE, IO_LOW },
 [IO_USART2_RX] = { IO_ALTERNATE_FUNCTION, IO_AF1, IO_PUSH_PULL, IO_VERY_HIGH_S, IO_NONE, IO_LOW },
 [IO_USER_LED] = { IO_GPIO_OUTPUT, 0, IO_PUSH_PULL, IO_VERY_HIGH_S, IO_NONE, IO_HIGH },
 [IO_MCO] = { IO_ALTERNATE_FUNCTION, IO_AF0, IO_PUSH_PULL, IO_VERY_HIGH_S, IO_NONE, IO_LOW }
};

 

The results obtained using the HAL library and my own wrapper are the same.

I was probing the right pins according to the schematics, but what looked strange to me is the signal I was getting on my probe.

tek00000.png

 I expected a noisy rectangular signal, and this looks a bit more like a sine wave to me.

I have the probe connected to CN9/PIN8 and I get the GND ref from CN6/PIN7.

undacmicAuthor
Associate II
January 16, 2025

UPDATE

I also managed to get the standard deviation of the period cycle of 103 ps for a 64MHz frequency and will follow the same process described in the FPGA implementation here (An embedded true random number generator for FPGAs ) for my RNG implementation and then test it against NIST SP-800 statistical tests.

 

tek00001.png