When trying to frequency hop on the main PLL, I observe a lock time of ~150ms. This seems quite high and I can't find any more information in the datasheet on the matter. Is anyone able to verify the PLL lock time?
Hello,
In case the PLL is already locked to a certain frequency re-locking to a new frequency depends on the frequency and the frequency hopping step, nevertheless the locking time should be below 500µs.
For start-up the locking time is longer and again depending on the target frequency. Expect a locking time around 800µs.
All above is concerning cases at which the VCO segment is manually chosen.
In case a procedure which is using the Automatic VCO Range Selection (A4h) command is implemented, then the overall locking time is longer since the command A4h itself is taking up to 6 ms to complete, reporting the optimal VCO segment.
Cheers,
B
Enter your E-mail address. We'll send you an e-mail with instructions to reset your password.
