ST25DV04KC LPD Pin Voltage Anomaly (~2.1V Intermediate Level) with 4.7kΩ Pull-up Resistor

[jokes]

Dear ST Support Team / Community Engineers,

I am currently integrating the ST25DV04KC into my design. The VCC and LPD pins are connected to an MCU, which controls the transition between normal operation and ultra-low power mode.

During testing, I observed an abnormal voltage behavior on the LPD pin:

• System Voltage: 3.1V
• Pull-up Resistor: 4.7kΩ (External)
• Issue: During the level switching transition, the LPD pin voltage stalls at an intermediate level of approximately 2.1V, instead of rising cleanly to VCC. This intermediate voltage persists long enough to potentially cause logic uncertainty for the MCU.

Troubleshooting Steps Taken:

1. Reduced Pull-up Resistance: I replaced the 4.7kΩ resistor with a 1.2kΩ resistor. This change successfully eliminated the intermediate voltage plateau, and the signal now transitions correctly.
2. VCC Disconnection Test: I also noticed that disconnecting the VCC supply seems to eliminate this phenomenon as well.

My Questions:

1. What is the physical mechanism causing this ~2.1V intermediate level when using a 4.7kΩ pull-up? Is it related to internal leakage currents or specific input threshold characteristics of the LPD pin during state transitions?
2. Is the 2.1V level considered a valid high/low state, or does it pose a risk of undefined logic states for the driving MCU?
3. Do you recommend a maximum pull-up resistance value for the LPD pin to ensure robust operation, especially given that 4.7kΩ seems to be borderline in this scenario?

Any insights or datasheet clarifications regarding the LPD pin's input impedance and leakage current specifications would be greatly appreciated.

Best regards,

 

[JL. Lebon]

Hello, 

This is explained in the section “2.2.2 Low power down (LPD) “ of the datasheet: 

When this pin is set high, the internal pull-down is deactivated if the external impedance applied on it does not exceed 5 kΩ. The LPD pin is internally pulled-down.

The internal pull-down is there to allow normal operation of the tag if the LPD pin is left unconnected. It is automatically deactivated (to avoid consuming in the pull-down) if the external impedance that drives high is low enough (e.g. drived by an MCU GPIO output). But with the 4.7kohm pull-up, your external impedance is not low enough to completely deactivate the internal pull-down mechanism. The datasheet states 5kohm and you are close to this limit, hence the intermediate 2.1V you see.

 

Best regards.

[jokes]

Hello,

Thank you for the detailed explanation. Before we consider switching to a GPIO-driven solution, we would like to evaluate whether our current hardware setup is acceptable. Could you please clarify the following three points?

1. Validity of the Intermediate Voltage: Is the ~2.1 V level observed on the LPD pin considered a valid logic state? Specifically, does maintaining this intermediate voltage have any negative impact on the ST25DV chip’s operation, reliability, or power consumption?
2. Recommended Pull-up Resistance: If we continue to use a passive pull-up resistor, what value do you recommend? We aim to use the highest possible resistance value to minimize current consumption while still ensuring reliable operation.
3. Current State Assessment: Our primary goal right now is to determine if the current design (with the 4.7 kΩ pull-up) is viable. We want to confirm if this configuration can be accepted before committing to a PCB change or firmware update to drive the pin via GPIO.

Looking forward to your advice.

Best regards,

[JL. Lebon]

Hello, 

Answers to your questions are in the table 249 of the datasheet:

VIL_LPD maximum value is specified at 0.2VCC max
VIH_LPD minimum value is specified at 0.85VCC min

So, if your supply voltage is 3.1V, the maximum valid input low level for LPD is 0.62V and the minimum input high voltage is 2.63V. This means that with 2.1V you are in an undefined zone and the behavior can’t be predicted.

Concerning the pull-up resistance value, you can use the 1.2kohm if it works correctly. When NFC_LPD signal is high (or HiZ) the current on the pull-up will be very low considered that the LPD pin will present a very high impedance in series with the 1.2kohm pull-up (the internal pull-down is disengaged in that case). When NFC_LPD is driving low you will off course consume current in the 1.2Kohm resistor.
Having the LPD pin directly connected to a GPIO (without a pull-up) may be an option: when LPD must be enabled, the GPIO should drive high (power consumption will be very low as LPD impedance will be high in that case). When LPD must be disabled, the GPIO can be set in HiZ as the internal LPD pull-down will tie the pin low or can dive low.

Best regards.