Power management & timing parameters of the ST25DV chip
@JL. Lebon
Dear ST Engineer,
Thank you for your previous assistance. I have two further technical questions regarding the power management and timing parameters of the ST25DV chip:
1. Concerning the VCC Rise Rate Limitation The datasheet states in the Power Management section: "When the power supply is turned on, VCC rises from VSS to VCC. VCC must not rise faster than 1 V/μs."
In my ultra-low-power application, I connect the ST25DV VCC pin to a MCU GPIO pin, accompanied by a 10nF decoupling capacitor. During actual measurement, I observed that the initial rise rate of VCC is approximately 2 V/μs (specifically, the rise time from 0V to 1V is about 0.44 μs, as shown in the attached waveform).
Could you please clarify:
- What is the underlying physical reason or risk consideration for this 1 V/μs limit?
- Given my specific hardware configuration (GPIO-driven + 10nF cap), is the observed rise rate of ~2 V/μs acceptable for reliable operation, or does it pose a potential risk to the chip?
2. Concerning the tMINCD Parameter Regarding the parameter tMINCD mentioned in the datasheet:
- Data Transmission Window: The datasheet specifies
tMINCDwith a MAX value of 1 ms. Does this imply that no data transmission can be initiated within the first 1 ms after power-up?- Since I am aiming to minimize the total communication time in my application, I would like to know if this 1 ms duration is a fixed worst-case scenario or if there is any possibility/method to shorten this mandatory waiting period.
Your insights on these points would be greatly appreciated.
Best regards,