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GWang.5
GWang.5
Associate
November 17, 2022
Question

When using DMA to tranfer data of UART, what will happen if Bit20 TRBUFF of DMA_SxCR is not set?

  • November 17, 2022
  • 6 replies
  • 3672 views

I am using the UART of STM32H747,with DMA transfering data. There is a Note in the reference manual about DMA_SxCR register:

0693W00000WIb6AQAT.pngAnd in the Errata sheet of STM32H743, it says:

0693W00000WIb6tQAD.pngWhat does a concurrent transfer mean? Will the DMA channel transfering UART data be locked? What are chances the DMA channel be locked? How can I make the lock happen in my own project?

This topic has been closed for replies.

6 replies

RomainR.
RomainR.
ST Employee
December 1, 2022

Hello GWang.5 (Community Member)

Welcome on ST Community.

A concurrent transfer means DMA is performing another transfer request with other peripheral than USART. 

DMA protocol is based on state machine between peripheral request and DMA acknowledge. The peripheral request is cleared when dma acknowledge is asserted.

When using TRBUFF=0, if the application uses several dma transfer with several peripheral (for example ADC and USART). If DMA acknowledge take longer time than expected to clear ADC request, and if at this time an USART request appears, USART transfer will be not served, and DMA stream may stay locked.

With TRBUFF=1, the same issue will not happen because the ADC DMA ack is cleared immediately after AHB transfer completion is ready. So, if USART send DMA request, it will be served.

TRBUFF bit acts as workaround.

Best regards,

Romain

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GWang.5
GWang.5Author
Associate
December 3, 2022

Hello Romain

Thank you for your answer, but I still have some questions. For clarity, I quote your answer in "bold italic" style.

​

Q1: Does "The peripheral request is cleared when dma acknowledge is asserted." mean "The peripheral request is cleared when dma acknowledge is asserted set"?

Q2: If the answer to Q1 is yes, should "ADC DMA ack is cleared immediately after AHB transfer completion is ready", be "ADC DMA ack is cleared set immediately after AHB transfer completion is ready"? Or it can't clear the ADC request, and "if at this time an USART request appears, USART transfer will be not served, and DMA stream may stay locked."

Best regards,

GWang.5

RomainR.
RomainR.
ST Employee
December 5, 2022

Hello GWang.5.

To clarify this:

Q1 -> Answer1:

Yes, peripheral request  is cleared when DMA acknowledge is set.

Refer to RM0399: 16.3.4 DMA transactions:

Q2 -W Answer2:

The ADC DMA ack is cleared immediately after AHB transfer completion is ready.

Best regards,

Romain,

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