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Natan Stec
Natan Stec
Associate II
December 8, 2020
Solved

How to use BDMA in STM32H7?

  • December 8, 2020
  • 13 replies
  • 11116 views

I am trying to read signals from digital MEMS microphones via DFSDM peripheral and transfer it to memory with DMA on STM32H7A3. I found out that 4 channels are handled by DMA and remaining 4 with BDMA. Now I can't figure out how to get this BDMA to work.

Below I placed screenshots of Cube configuration and initialization of DFSDM with DMA. I suspect that the problem can be with memory configuration in linker script, since DMA and BDMA has not access to the same memory sections. Do someone have idea if my assumptions are correct and can suggest what should I do to get it to work?

0693W000006Ey0IQAS.png0693W000006Ey0NQAS.png 0693W000006Ey0XQAS.png

This topic has been closed for replies.
Best answer by Natan Stec

Hi Ons,

Unfortunately, we've found out that BDMA doesn't have parallel channels. So even if it would start working it wouldn't suit our needs. Thank You very much for your support.

13 replies

Ons KOOLI
Ons KOOLI
Associate
December 8, 2020

Hi Natan Stec,

Can you please share your .ioc file.

You also can refer to the STM32CubeH7 Firmware where you can find DFSDM examples.

Best Regards,

Ons.

Natan Stec
Natan StecAuthor
Associate II
December 8, 2020

Hi Ons,

Thank you for your answer.

I will check examples in second and check if there is something relevant.

Natan Stec
Natan StecAuthor
Associate II
December 8, 2020

Unfortunately in those examples only 2 channels are being used which are working with DMA. Whereas I have a problem with DFSDM channels 5-8 which uses BDMA.

Ons KOOLI
Ons KOOLI
Associate
December 9, 2020

Hi Natan,

It seems like your RAM starts from 0x2000000 which is the DTCM address , and which is not accessible by DMA or BDMA.

Try to refer to the reference manual and put your code in an accessible memory by DMA or BDMA (AXI SRAM).

Best Regards,

Ons.

Natan Stec
Natan StecAuthor
Associate II
December 22, 2020

Hi,

I've put this struct in memory AHB SRAM1, which is accessible by both DMA and BDMA according to the reference manual. But it, unfortunately, didn't make a difference.

Now I'm wondering if transfer via BDMA requires some different kind of handling. Because now even though I configured it in Circular Mode, BDMA1_IRQHandler fires only once.

Now I'm starting all channels with the same HAL function (filter 0,1,2,3 uses DMA and filter 4 uses BDMA).

HAL_DFSDM_FilterRegularStart_DMA(&hdfsdm1_filter0,
			(int32_t*) &mic[0].sig_raw, FULL_BUFF_SIZE);
HAL_DFSDM_FilterRegularStart_DMA(&hdfsdm1_filter1,
			(int32_t*) &mic[1].sig_raw, FULL_BUFF_SIZE);
HAL_DFSDM_FilterRegularStart_DMA(&hdfsdm1_filter2,
			(int32_t*) &mic[2].sig_raw, FULL_BUFF_SIZE);
HAL_DFSDM_FilterRegularStart_DMA(&hdfsdm1_filter3,
			(int32_t*) &mic[3].sig_raw, FULL_BUFF_SIZE);
HAL_DFSDM_FilterRegularStart_DMA(&hdfsdm1_filter4,
			(int32_t*) &mic[4].sig_raw, FULL_BUFF_SIZE);

Unfortunately, I wasn't able to find any examples of using BDMA.

Ons KOOLI
Ons KOOLI
Associate
December 23, 2020

Hi Natan,

According to the reference manual, "AHB SRAM1 is accessible by all system masters except BDMA through D2 domain AHB matrix." (p135)

Therefore, I don't think that the use of AHB SRAM1 is a good choice.

Best Regards,

Ons

Natan Stec
Natan StecAuthor
Associate II
December 28, 2020

Hi Ons,

I can't find such info in the reference manual you linked for my MCU - STM32H7A3.

Here is page 135 from this manual.

0693W000006GxPXQA0.png 

From this words:

"embedded system SRAM is divided into up to six blocks:

• CD domain, AXI SRAM:

– AXI SRAM1 mapped at address 0x2400 0000

– AXI SRAM2 mapped at address 0x2404 0000

– AXI SRAM3 mapped at address 0x240A 0000

All AXI SRAMs can be accessed by all system masters through the AXI bus matrix except BDMA1 and BDMA2.

• CD domain, AHB SRAM:

– AHB SRAM1 mapped at address 0x3000 0000

– AHB SRAM2 mapped at address 0x3001 0000

All the AHB SRAMs can be accessed by all system masters through the CD AHB matrix except for BDMA2."

I deduced that I should put data in AHB SRAM, as I am using BDMA1.

Statement you just mentioned "AHB SRAM1 is accessible by all system masters except BDMA through D2 domain AHB matrix." I could find in the reference manual for MCU - STM32H750VBT6.

Natan Stec
Natan StecAuthorBest answer
Associate II
March 16, 2021

Hi Ons,

Unfortunately, we've found out that BDMA doesn't have parallel channels. So even if it would start working it wouldn't suit our needs. Thank You very much for your support.

Ons KOOLI
Ons KOOLI
Associate
March 16, 2021

Hi Natan Stec,

Can you please select your answer as best ? Since it is the best answer, BDMA (basic DMA) does not support parallel channels.

Best Regards,

Ons.

RUlstrup
RUlstrup
Associate
June 1, 2022

Hi all,

Know this is a dead post, but I found out there is a bug with the BDMA and DFSDM, where it do not put the BDMA into circular DMA setting after starting the DFSDM filter.

A dirty fix is forcing the register BDMA_CCRx into the correct configurations on line 719 in stm32h7xx_hal_dma.c. In my case the configurations would be:

((BDMA_Channel_TypeDef  *)hdma->Instance)->CCR = 0x2AAE;

(look up STM32H7A3 reference for more information on that register)

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