Is it possible to trigger an event with the same timer used for a PWM generation?

TIM1 is different from other timers in that it has a separate interrupt for Capture/Compare, and a different one for Update and other events. Make sure you have enabled the latter (TIM1_BRK_UP_TRG_COM_IRQn) and that the ISR is appropriately named, too.

Also read out and check the TIM registers, mainly if TIM1_DIER.UIE is set.

JW

Hello Waclawek.jan and thank you for your answer.

(TIM1_BRK_UP_TRG_COM_IRQn) was already enable.

I have set the UIE bit of TIM1_DIER which i did not found configured at all, but it changes nothing.

And what do you mean by "the ISR is approriately nammed" ?

As i was worknig exclusively with HAL functions thanks to CubeMX and i was not really understanding the fundamental aspect of the way it works, i have decided to run through the datasheet (DMA, Interrupts and Events, ADC and finally timers chapters) in order to have the knowledge for what i need in my project.

My english is not my native language and as i am quite new in STM32 microcontroller, i have some basic questions. It would be great if you could bring lights on it (thanks in advance :smiling_face_with_smiling_eyes: )

I know it will take some time to answer, but i think it will be helpfull for the next new developpers =)

1.DMA chapter:

• A peripheral must send a request to DMA to launch the data transfer:
  • For example: to launch ADC acquisition with DMA at a fix frequency, i must set a timer triggering an interruption at the fix frequency (TIM1_TRGO or TIM1_CC4 or TIM3_TRGO or TIM14_TRGO), which will launch an ADC acquisition followed by a request sent to DMA which will launch the transfer of the converted data to memory?
  • In more details:
    • DMA channel can be enable thanks to EN bit 0 ofr DMA_CCRx which activate the DMA channel
    • DMA_CSELR register is for DMA request mapping, for example: ADC on channel 1.

=> Which of the above condition trigger the DMA transfer ? As i understand the DMA channel Configuration sequence code exampe,

I guess DMA channel should be enable first and the DMA request mapping triggers the DMA. Is that correct ?

2.Interrupts and Events chapter:

• What's the difference between NVIC and EXTI (this is not clear for me):
  • EXTI is used for GPIO events/interruptions wheareas NVIC couldn't.
  • EXTI can be used to wake up the uC whereas NVIC couldn't
  • Both EXTI and EXTI can be used with internal peripherals
  • EXTI are parts of the NVIC ?
  • In which case should i use NVIC or EXTI ?
• What is the difference beween EVENT and interrupts? I see that for EVENT, there is no need to clear EXTI peripheral interrupt bit and the peripheral NVIC IRQ channel bit after a uC wake-up.
• Configuring the mask bit in the EXTI_IMR or EXTI_EMR register means to set the bit corresponding to the good GPIO. For example: i want an interruption trigrered by PB1. I should first put 0010 into EXTI1 bits of the SYSCFG_EXTICR1 register and set the bit #1 of the EXTI_IMR. Is that correct?
• What happens if i set up a rising AND failing trigger at the same time for that PB1 interruption example, both will be detected ?
• The EXTI_SWIER register let us the user to trigger an interrupt/event by itself instead of an automatic trigger by the peripheral. Is that correct ? This set the corresponding into the EXTI_PR register. What's the point of doing a not automatic triggered interruption/event ?
• What's the point to send a request to DMA by a Timer? what could be the data transfered from one to the other except the counting value ? I see for PWM, that it could send duty cycle or period with DMA but i still don't get the point

3.ADC chapter

• When we want the ADC to be triggered thanks a timer, the ADC should be configured for it and the ADCSTART bit must set manually as a prerequisite to let the ADC be triggered by the timer. Is that correct?
• I see that if DMA has reached the last DMA transfer, a DMA_EOT interrupt occurs . But I don't see such a bit called this way in the DMA chapter. Is it the TCIFx bit of DMA_ISR register ?
• Moreover, to let the ADC makes new request to DMA after a DMA_EOT interrupt, the CTCIFx bit of DMA_IFCR must be set. Is that correct ?
• I see on Single conversion sequence code example - Software trigger that the scan direction is made after the conversion itself. Is that a mistake that it is not done before the conversion?

4.For the Timers part, i am still studying..:anxious_face_with_sweat:

Thank you ,

> I guess DMA channel should be enable first and the DMA request mapping triggers the DMA. Is that correct ?

Yes. But ADC presents an extra complication, maybe as an initial experiment, you may want to do a timer-triggered transfer, maybe from memory to GPIO or other TIM.

Try using it to blink a LED without any software running in main loop, only initializing peripherals. I may have some examples in that direction on efton.sk.

Doing that exercise will maybe answer your "why".

> EXTI

NVIC is part of processor core handling all interrupts. EXTI only interface the pin-related interiors, plus some few others which are wakeup related. Both edges generate interrupt, if you are able to process them fast enough.

>DMA_EOT

I don't use Cube not any other "library" exactly because they do these unnecessary renames. Cube is open source so you can look these things up yourself.

> DMA_IFCR

That's a register to *clear* already set flags.

>studying..:anxious_face_with_sweat:

The key is to both read and experiment. After reading about some feature, write a simple test program to verify if you've understood correctly what you've just read.

JW