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LDoes
LDoes
Associate II
October 6, 2020
Solved

STM32G474 ADC erratic measurements when using synchronous clock source

  • October 6, 2020
  • 1 reply
  • 1145 views

Hi,

I'm measuring a buffered voltage using injected conversions, triggered by a timer. I've limited the frequency of the ADC to F_adc < F_adc_hclk/4 as mentioned in the reference manual.

When I use the synchronous clock (ADC_CLOCK_SYNC_PCLK_DIV4) I get some erratic measurements when compared to the asynchronous clock (ADC_CLOCK_ASYNC_DIV4). I find this to be strange as both my AHB clock and SYSCLK are running at the same frequency (160MHz).

I would like to use the synchronous clock as this is recommended by ST when using timers as ADC trigger. Does anyone have an idea how to fix/circumvent this problem?

This topic has been closed for replies.
Best answer by Igor Cesko

Hi LDoes ,

It seems that the problem is in ADC clock speed - please check if the asynchronous clock for ADC has the same frequency as synchronous clock. Because asynchronous clock can come from PLL and some dividers defined in RCC registers.

From attached figure (incorrect ADC data are "locked to some value") it seems that ADC is either running on fast clock (in case of sync clock) or there is problem in PCB design - decoupling of VREF+ pin. Probably the sync clock is correct (40 MHz) - most probably the problem is in VREF+ decoupling. The VREF+ pin must be well decoupled: capacitor (100nF + 1uF) very very close between VREF+ and VSSA pins. Please try to improve the decoupling of the VREF+ pin. Decreasing ADC frequecy also helped - you can try to decrease system clock to 80 MHz (to decrease ADC clock to 20MHz).

Regards

Igor

1 reply

Igor Cesko
Igor CeskoBest answer
ST Employee
May 27, 2021

Hi LDoes ,

It seems that the problem is in ADC clock speed - please check if the asynchronous clock for ADC has the same frequency as synchronous clock. Because asynchronous clock can come from PLL and some dividers defined in RCC registers.

From attached figure (incorrect ADC data are "locked to some value") it seems that ADC is either running on fast clock (in case of sync clock) or there is problem in PCB design - decoupling of VREF+ pin. Probably the sync clock is correct (40 MHz) - most probably the problem is in VREF+ decoupling. The VREF+ pin must be well decoupled: capacitor (100nF + 1uF) very very close between VREF+ and VSSA pins. Please try to improve the decoupling of the VREF+ pin. Decreasing ADC frequecy also helped - you can try to decrease system clock to 80 MHz (to decrease ADC clock to 20MHz).

Regards

Igor

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