What is the min/max skew on the counter outputs for the STM32F107RC?

Hello all,

I looking to use a STM32F107FC as a digital waveform generator. The system clock would be 28MHz and so would the APB bus feeding the timers. I plan to have TIM4 drive an output with a 14MHz clock signal and act as a master for TIM3. TIM3 would be (effectively) clocked by TIM4 and drive four outputs, all using PWM in TIM3 in a fixed cycle.

Of course, there's going to be some edge skew between the clock from TIM4 and the outputs driven by TIM3 (and within the TIM3 outputs), so things will need to be re-clocked. The current plan is to use the falling edge of the TIM4 output. However, this relies on the five signals having a edge skew within 25 to 30nsec (the outputs will all be high powered with less than 30pF for a load capacitance). I checked the spec and the reference manual for the STM32F107FC, but there's no mention of signal skew. I've also searched the forums and the app notes with no luck. Anyone have any ideas how to get the info or know what the values are? Otherwise I'll have to start adding parts to the design like a PLD. Using the MCU would be cleaner though.

Thanks!