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DGran.1
DGran.1
Visitor II
Aug 18, 2020 10:01 PM UTC
Question

What is the maximum GPIO to memory DMA throughput on a STM32-H743ZI clocked at 480 MHz when running 1 or 2 channels simultaneously?

I would like to attach 2 high speed A/Ds connected via parallel GPIOs and run them at 50 MHz each, or 100 MHz aggregate.  One A/D is 12 bit and the other is 8 bit so I could take advantage of FIFO packing on the memory side. The capture buffer size would be 10k for each channel.

Is this throughput possible? If so, what would be the best way to configure and trigger the 2 DMA channels?

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1 reply

waclawek.jan
waclawek.jan
Super User
Aug 19, 2020 6:14 AM UTC

I doubt this can be achieved. AHB4 where GPIOs sit is clocked at 240MHz max, and the closest BDMA is the single-port DMA, IIRC min. 6 cycles per transfer.

IMO there's no way to get this throughout in any way, so you might want to build an external grabber from an FPGA.

I may be wrong, I don't use the H7.

JW

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