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SRibo
SRibo
Associate II
April 28, 2020
Question

STM32L471 ADC1 unstable calibration and accuracy at 80Mhz. Stable at 40Mhz.

  • April 28, 2020
  • 4 replies
  • 1336 views

Hello,

I'm working on a project involving the STM32L471 device clocked at 80Mhz (External

crystal oscillator with internal PLL).

We are using ADC1, also clocked at 80Mhz (CKMODE = 0x01)

We are noticing an issue concerning the calibration (and the consequent readings accuracy).

The ADC calibration result gives different result at every board power up (calculated value in the CALFACT register is different at after each calibration). Also recalibrating the ADC without powering off the board gives different CALFACT result.

This lead to incorrect readings accuracy (INTVREF reading is wrong).

Note that ADC readings (12 bit) are incorrect but very stable. AVDD is stable and noise free, and the VREF+ signal is connected to a precision voltage reference (3V).

We noticed that if we reduce ADC clock frequency to 40Mhz (CKMODE = 0x10) all works fine. Calibration gives always the same result, and readings are very accurate.

We checked on the datasheet, and it seems that ADC can be clocked at 80Mhz. Is this true? Or for some reasons ADC doesn't work properly at 80Mhz?

Thank you.

Regards.

This topic has been closed for replies.

4 replies

TDK
TDK
April 28, 2020

Reducing the ADC clock speed by 2 will also increasing the sampling time of the ADC by 2. Likely your sample times are not long enough to produce stable results under 80 MHz.

Note the VREFINT has a minimum sample time given in a datasheet.

ADC calibration will vary a bit each time you run it. For me, I saw about 5 counts variation. Presumably one could lower this with a more stable supply. Note that no power rail or voltage reference is "noise free".

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SRibo
SRiboAuthor
Associate II
April 28, 2020

The VREFINT sampling time during the calibration process is automatically handled by the ADC. It's not configurable.

Timings during the calibration process (for example for internal regulator stabilization) are respected in our firmware.

I've also tried to follow instructions step by step, but the result is always the same:

At 80Mhz, I obtain calibration values (CALFACT register) randomly between 50 and 59 (poor accuracy).

At 40Mhz, I obtain always the same value (59 dec) and the ADC accuracy is very high. (VREFINT reading error is more or less 1mV).

Note: VREFINT sampling time is set to the maximum value.

SRibo
SRiboAuthor
Associate II
April 29, 2020

I would like to add a new information:

I tried to clock the ADC from PLLSAI1 clock.

Also using this clock source at 80Mhz, calibration is unstable.

Lowering down the ADC clock to 72Mhz, calibration become stable (always the same value, 59 dec).

Regards.

SRibo
SRiboAuthor
Associate II
April 29, 2020

Hi Mikhail,

My issue is related to the ADC self calibration. No sampling time is configurable or involved during the self calibration process.

At 80Mhz the calibration offset (CALFACT register, that contains the self calibration result) is not stable. After each calibration I get

different values from 50 to 59 (I tried also 100 calibrations in a loop without powering off the device, to check the variance of CALFACT).

In this condition, acquisition error is high (up to 8/10mV)

Starting from 72Mhz to lower frequencies, CALFACT is stable and always the same value (59 dec). In this condition, acquisition error is more or less 1mV.

The reference signal used to test the ADC accuracy is the INTVREF. Sampling time set to the maximum allowed, stabilization time always respected.

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