Question regarding power scale mode and frequencies in RM0431 and DS11853

I'm working on a course and until now all my examples worked fine using HSI as the system clock. But now I'm trying to get an ST7735 screen attached to SPI to work. The screen screen seems to require its hexadecimal instructions bitwise and the parameters following the instruction to be the next bits right after the last bit of the instruction has been sent. In the mean time between sending instructions and data, switching of other pins seems to be required.

Because I'm working with seperate functions to send commands and data, which also take the switching of the other lines to their account, I assume the execution time required for exiting one function and starting the next one takes too many cycles between data and command and therefore causing a gap between the instruction and the subsequent data being sent over SPI to the LCD controller.

Enabling prefetch and the Art accelerator combined with configuring the PLL to run at 176 mHz and using this device as system clock seemed like the right thing to do for me in this particular case. However, I'm not absolutely sure wether or not I'm interpreting the information from the corresponding tables and chapters in the Reference manual and the Datasheet right.

Paragraph 3.3.2 "Read access latency" from RM0431

Paragraph 4.4.1 "PWR Power control register (PWR_CR1)" from RM0431

Table 16 "general operating conditions" from DS11853,

Table 17 "limitations depending on the operating power supply range" from DS11853

In paragraph 3.3.2 in the note above Table 15 I see:

when VOS[1:0] = 0x11 the maximum value of Fhclk is 180 mhz.

In paragraph 4.4.1 "PWR Power control register (PWR_CR1)" I found 0x11 stands for Scale 1.

In paragraph 4.4.1 I see that by configuring the VOS bits I can set the device to work at three different power scales, 1, 2 and 3. Regarding this note and PWR_CR1 description, scale 1 is presumably the required setting for my purpose.

From here on and up until further down the road I can only work on with assumptions, because the manual doens't provide me with the hooks required for me to make me sure of my case anymore. Not unless the required information lies in other chapters that are out of my reach of comprehending, just because I lack the theoretical background on the electronics part of the MCU.

Anyways, in table 15, right below the note I just mentioned I see four collumns showing wait states for four different voltage settings. I only see three power scale options, but I assume this might have to do with enabling and disabling the power regulator.

Well, now, The Table 16 from the product datasheet shows me:

1.2 V internal voltage on Vcap_1 and Vcap_2 pins.

power scale 3 max 1.20 v max 144 mHz no overdrive

power scale 2 max 1.32 v max 168 mHz no overdrive

power scale 1 max 1.40 v max 180 mHz no overdrive

Using just this information got me stuck for a while. Bacause table 15 in paragraph 3.3.2 "Read access latency" shows me

Voltage ranges 1.8v to 2.1v / 2.1v to 2.4v / 2.4v to 2.7v and 2.7v to 3.6v. Except for 1.8v to 2.1v 176mHz is found in the tree other collumns, every time corresponding to a different amount of wait states, 6, 7 or 8 wait states. I can't tell which one to choose. Besides that, the voltages in table 15 from the reference manual don't match the voltages described in table 16 from the product datasheet.

After this I decided to search for all occasions where I could find more information on Vcap_1 in the datasheet, but this didn't provide me the information required for moving on. I remained stuck until I accidentally scrolled down a bit to the next table in the product datasheet, table 17 "Limitations depending on the operating system power supply range" where I thought I found values that could somehow relate to the information I discussed before, however I didn't find any description regarding wether or not my assuptions are right. The operating power supply ranges VDD values in this table seemed to match the voltage ranges used in the header of Table 5 "The number of wait states according to CPU clock (HCLK) frequency."

After more closely inspecting the voltages mentioned in table 15 and comparing them to table 16 of the datasheet, I came up with the next theory.

is VDD equal to Vcap_1 plus Vcap_2?

This is the only thing I could come up with to get the different voltages described in the different tables to make sense to me.

If I'm right about this, I can move on and program the Flash latency to 7 wait states. This math seems logical to me, but I can find nothing in the manual that confirms these conclusions. I found no section that tells me for sure that I am right in interpreting these values.

I cannot find anywhere what voltages the VOS bits in PWR_CR1 relate to nor what power will come from what pins by changing the VOS power mode.

Neither can I find anything about VDD realy being related to Vcap_1 plus Vcap_2 in any sort of way, unless I have to retreive this information from the electro chart diagrams in the datasheet, but thats out of my league because I am a programmer and not an electronics engineer.

Is there anyone who can confirm wether or not I'm right here? The fact that this regards voltages I am a bit concerned of breaking the device, but I do want to move on. The relations between the different voltage levels and powerscales I described earlier on do seem to relate but I need to have this confirmed to be sure.