ST please document in RMs, which interrupts are level/pulse triggered

It could be conveniently added to the vector table in Interrupts and Events chapter in the RMs.

One reason why I am asking for this - besides the fact that this is quite a substantial information which ought to be present in documentation - is, that avoiding using pulse-triggered interrupts (and most interrupts in STM32 are level-triggered so this is usually viable) is one of the strategies to cope with the Cortex-M4 erratum 838869 Store immediate overlapping exception return operation might vector to incorrect interrupt.

Thanks,

JW