Use STM32H7 ETM without debugging tool

Tends to be the domain of debugger writers, ARM should have app notes, but presupposes familiarity with HW/SW at this level.

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0242b/DDI0242.pdf

Others on the forum have built trace HW, so might have some specific insight.

@Bob Boys​ any thoughts on the internal mechanics ARM can share?

Thank you Clive. So I've read again the related section in the ref Manual. What I deduced is that ARM provides several ways to store the execution trace and among them ST chose to implement the ETF.

This ETF can be setup in Circular Mode, which looks like the mode I need:

"3. Circular buffer mode

The trace memory is used as a circular buffer. Trace data is captured into the Trace

memory starting from the location pointed to by the write pointer register. Even when

the trace memory is full, incoming trace data continues to be overwritten into the trace

memory until a stop condition occurs.

In this mode, the ETF stores the trace data on-chip, so the trace log size is limited to

that of the ETF SRAM, 4 Kbytes in this case. Being a circular buffer, if the FIFO

becomes full, incoming trace data overwrites the oldest stored data and the oldest

stored data is lost. Therefore the contents of the trace buffer represent the most recent

activity of the processor, up to the point when the buffer was stopped, rather than all

the activity since the trace was started.

There are three possible methods to read out the buffer contents once the trace stops:

– via the Trace port - with the TPIU enabled, the contents of the buffer are output

over the Trace port. This can be done by setting the DRAINBUF bit in the

ETF_FFCR register.

– via the Debug port - the debugger can read the buffer via the RRD register that is

accessible over the system APB-D.

– by software - the processor can read the buffer via the RRD register, since the

APB-D is accessible from the system bus."

The reference manual also gives the description of the ETF registers. I will try to implement the functionality based on this but I find the documentation ia bit "light" to do so without wasting days. So I would still appreciate tips, code examples or application notes.

So I've based my implementation on two documents, the section on ETF in STMicro STM32 reference manual and ARM's Trace Memory Controller Reference Manual. In the latter in particular there is a sequence to setup the ETF:

Circular Buffer mode

The recommended standard usage model in this mode is as follows:

1. Wait until TMCReady is equal to one.

2. Program the MODE Register for Circular Buffer mode.

3. Program the FFCR Register. ARM recommends that you set the TrigOnTrigIn,

FOnTrigEvt, StopOnFl, EnTI, and EnFt bits. This enables formatting, inserting a trigger

when a trigger is observed on TRIGIN, and following a delay corresponding to the value

of the TRG Register, flushing and then stopping the TMC.

4. Program the TRG Register, to control the amount of buffer to be dedicated to the period

after a trigger is observed.

5. Set the TraceCaptEn bit in the CTL Register. This starts the trace session.

6. Wait until TMCReady is equal to one. This indicates that the trace session is over.

7. Read the contents of the trace buffer by performing successive reads to the RRD Register,

until the value 0xFFFFFFFF is returned.

8. Clear the TraceCaptEn bit in the CTL Register.

The notion of triggers is more or less incomprehensible so I've stupidly written the registers as described without really understanding what's going on.

But actually I can't go very far in my debug: it looks like the ETF registers are not accessible (they're all read to 0 either through the debugger or through my embedded software). There is probably an "enable" bit somewhere to activate or clock the TMC or ETM or ETF or who knows what macrocell.

Here is the piece of quick and dirty code I tried, every register is read to 0 and not modified by this code

HAL_Init();
SystemClock_Config();
MX_GPIO_Init();
MX_USART3_UART_Init();
 
// enable ETM trace
*ETM_PRGCTRL = 1;
 
// enable ETF circular mode
*ETF_FFCR = 0x00001123; // ARM recommends to set bits TRIGONTRIGIN FONTRIGEVT STOPONFL ENTI AND ENFT
*ETF_TRG = 16; // number of 32 words to capture
*ETF_CTL = 1; // enable trace
 
i = 1000;
while(i--)
 asm("nop"); // ******** processing just to fill the trace
 
while ( ((*ETF_STS) & (1<<2)) == 0 );
 
printf("*ETF_RRD=0x%x\r\n", *ETF_RRD);
printf("*ETF_RRD=0x%x\r\n", *ETF_RRD);
printf("*ETF_RRD=0x%x\r\n", *ETF_RRD);
printf("*ETF_RRD=0x%x\r\n", *ETF_RRD);
 
*ETF_CTL = 0; // disable trace

I've found this comment on the Segger forum:

"(...) unfortunately ST made the decision with the STM32H7 to "hide" some trace related modules behind the APB instead of AHB as it is usual for Cortex-M7. That way the generic trace init process becomes highly ungeneric."

ST people, could you comment on that ?

In which way is the H7 multicore ?

An interesting point to note: the ID registers of ETM can be read properly from the debugger (even without unlocking ETM_LAR). The ID registers of ETF are read to 0...

Great ! Just noticed that the STM32H7 ref manual is inconsistent on debug mappings !

So if I use the address 0x5C014000 I can at least read/write ETF registers properly.

Hello

Sorry to take so long to reply to this - it was Arm TechCon show time last week.

The best way to do this is to access the circular RAM and read it with your software.

This way you do not need external hardware to read the 4 bit + clk signals of the TracePort output.

This method has the advantage to track the instructions no matter how fast your CPU is running.

There are CoreSight registers you need to configure to get trace data stored in this buffer.

I believe the trace data is comprised of the program flow changes, not each individual instruction executred. You, like the debbugger, must reconstruct the executed instruction details. The timestamps are not output with every instruction - I am not sure of the rule used here.

A good way to see how the ETM trace works is to use Keil uVision (free eval version will work) and a ULINKpro (US$ 1,250).

Good luck !

Bob Boys

Arm

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 See RM0433 (Rev6), page 3104:

 https://www.st.com/content/ccc/resource/technical/document/reference_manual/group0/c9/a3/76/fa/55/46/45/fa/DM00314099/files/DM00314099.pdf/jcr:content/translations/en.DM00314099.pdf

Circular buffer mode

The trace memory is used as a circular buffer. Trace data is captured into the Trace

memory starting from the location pointed to by the write pointer register. Even when

the trace memory is full, incoming trace data continues to be overwritten into the trace

memory until a stop condition occurs.

In this mode, the ETF stores the trace data on-chip, so the trace log size is limited to

that of the ETF SRAM, 4 Kbytes in this case. Being a circular buffer, if the FIFO

becomes full, incoming trace data overwrites the oldest stored data and the oldest

stored data is lost. Therefore the contents of the trace buffer represent the most recent

activity of the processor, up to the point when the buffer was stopped, rather than all

the activity since the trace was started.

There are three possible methods to read out the buffer contents once the trace stops:

– via the Trace port - with the TPIU enabled, the contents of the buffer are output

over the Trace port. This can be done by setting the DRAINBUF bit in the

ETF_FFCR register.

– via the Debug port - the debugger can read the buffer via the RRD register that is

accessible over the system APB-D.

– by software - the processor can read the buffer via the RRD register, since the

APB-D is accessible from the system bus.

Hello

If you have a ULINKpro (or Segger J-Trace or IAR iJetTrace) you can observe a working ETM system to save time. You can examine various registers to see what works.

ULINKpro can also access ETB - although I have not tried it on your processor.

Bob Boys

Arm