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JuM
JuM
Senior
August 21, 2019
Solved

STM32G0 ADC clock. Max. asynchronous clock according to datasheet is 35 MHz. Is this (35 MHz) the input to PRESC or the output of PRESC ?

  • August 21, 2019
  • 3 replies
  • 3088 views

0690X00000AA0nIQAT.jpg

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Best answer by AScha.3

Yes, 32 MHz is okay, 64 not.

( The effective clock going to the ADC, after the prescaler. )

And set a sampling time, that's big enough to match the source impedance, see ds about that.

3 replies

Hl_st
ST Employee
October 31, 2023

The ACD clock limitation is behind the divider (in your picture marked as "Or this ?")

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raghul
Explorer
August 17, 2024

My question is in CubeMx Configuration the PCLK is 64MHz in my case STM32G070RB series and similarly to ADC clk configure at 64MHz.

if i configure ADC setting clock prescalar as synchronous clock mode  divide by 2 means -> ADC operate at 32MHz. It is within the range of ADC characteristics mention in datasheet (f_ADC =35MHz (max)) to get optimum performance of ADC.

If i choose ADC clock prescalar as asynchronous clock mode divide by 1 means -> ADC operate at 64MHz. This configuration may cause any adc performance problem?

 

AScha.3
AScha.3Best answer
Super User
August 17, 2024

Yes, 32 MHz is okay, 64 not.

( The effective clock going to the ADC, after the prescaler. )

And set a sampling time, that's big enough to match the source impedance, see ds about that.

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