Strange behavior writing to external SRAM

How's caching set up for that area in MPU?

JW

​I think Cache is disabled and commented out. Or is there any other Cache enabled by default on power up?

 /* Enable I-Cache---------------------------------------------------------*/
 //SCB_EnableICache();
 
 /* Enable D-Cache---------------------------------------------------------*/
 //SCB_EnableDCache();

I am new on this device. We used the STM32F439 before. The Manual of the H7 device have twice the amount of pages of the F439 device.

So I am (not) familiar with all details of this device.

I think there is a relation between AXI buswidth (64 bit) and connected Memory. One write command generates 64bit/MEMBUSWIDTH writepulses on the NWE-line.

But why can I write to a single Memory cell with the Debugger?

Best regards

  Christian

> is there any other Cache enabled by default on power up?

I don't know. I don't use the 'H7.

> The Manual of the H7 device have twice the amount of pages of the F439 device.

That's no excuse. ;)

And you should add all the pages of the generic Cortex-M7 documentation.

> I think there is a relation between AXI buswidth (64 bit) and connected Memory.

Well spotted.

From Supported memories and transactions subchapter of the FMC chapter:

The memory region MPU attribute must be configured as “Device�? or “strongly-ordered�?

in order to prevent issues on devices that do not have the byte select feature. As an

example, if byte accesses are performed to 16-bit memories with the MPU attribute set

to “Normal memory�?, the AXI transaction size is 64 bits and the FMC splits the

transaction into four consecutive accesses while only one access is expected instead

of four.

> But why can I write to a single Memory cell with the Debugger?

Debugger may have it's own way to access the buses. Again, I don't use the 'H7 nor any Cortex-M7 device so I'm not familiar with the intimate details of its architecture.

JW