SPI EOT interrupt triggered right after SPI enable

Hello,

I do some SPI communication, which in general works fine, now I want to get an interrupt at the end of transmission. I use only TxFifo, so TSIZE is left 0. It works fine to load some data into TxFifo via TXDR. Now I enabled SPI interrupt and set EOTIE. In isr I want to clear TXC, EOT and SUSP, which all correspond to EOTIE by writing all 1s to IFCR (but I only have TXC set).

The result I get is that the isr is executed right after enabling SPI and in SR I don't get TXC cleared which makes the isr being rentered over and over again or hanging in an endless loop checking the bit.

Here is my initialization code and my isr:

( #define SetBitMask(Var,BitMask) (Var|=(BitMask))

#define ClearBitMask(Var,BitMask) (Var&=~(BitMask))

#define BitMaskIsNOTClear(Var,BitMask) ((Var&(BitMask))!=0)

)

 SetBitMask (RCC->APB1LRSTR, RCC_APB1LRSTR_SPI2RST);
 ClearBitMask (RCC->APB1LRSTR, RCC_APB1LRSTR_SPI2RST);
 // enable SPI2 clk
 SetBitMask (RCC->APB1LENR, RCC_APB1LENR_SPI2EN);
 __DSB (); // needs to be here according to errata, to wait till periph clk is enabled
 // init SPI2:
 SetBitMask (SPI2->CR1, SPI_CR1_SSI);
 // SSI must be set, before SSM gets set and both must be set in master mode without external SS pin control
 // otherwise mode fault occurs and SPI will not work
 SetBitMask (SPI2->CFG1, SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0 | (16 - 1)); // clk and bit length
 SetBitMask (SPI2->CFG2, SPI_CFG2_AFCNTR | SPI_CFG2_SSM | SPI_CFG2_MASTER | SPI_CFG2_MIDI_0);
 
 SPI2->IFCR = 0xFFFFFFFF; // clear all pending ints
 __DSB (); 
 __ISB ();
 SetBitMask (SPI2->CR1, SPI_CR1_SPE); // enable
 // Enable the SPI2 Interrupt
 NVIC_SetPriority (SPI2_IRQn, IRQ_priority_SPI2);
 NVIC_EnableIRQ (SPI2_IRQn);
 
 SetBitMask (SPI2->IER, SPI_IER_EOTIE);
 SetBitMask (SPI2->CR1, SPI_CR1_CSTART); // start transmission whenever a byte is filled in TXDR
}
 
// ***************************************************************************
 
void SPI2_IRQHandler (void)
{
 if (BitMaskIsSet (SPI2->SR, SPI_SR_TXC))
 {
 // do something at the end of transmission
 }
 SPI2->IFCR = 0xFFFFFFFF; // clear all pending ints
 while (BitMaskIsNOTClear (SPI2->SR, SPI_SR_TXC | SPI_SR_EOT | SPI_SR_SUSP))
 {
 // it is hanging here, because TXC is not cleared, without the while loop the isr is reentered over and over again
 }
}
 

Why is this interrupt firing? RM0433 says it will be triggered, when master transmission is completed, but I did not send a byte before it is triggered.

Why can't I clear TXC or how do I have to do it?

Thanks a lot for any help

Kind regards

Martin