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francois06
francois06
Associate II
April 25, 2019
Question

Issue with SPI and SDIO using same DMA

  • April 25, 2019
  • 3 replies
  • 1180 views

Hello,

I'm working on an STM32F411 and I'm using two peripherals : one SPI and one SDIO.

The SPI is triggered every millisecond in a timer ISR and is using two DMA2 streams 0 and 2 in direct mode at a very high priority for TransmitReceive. Then, the DMA triggers an ISR at high priority at the end of transfer.

The SDIO is using DMA2 also but stream 3 with a FIFO at a medium priority and is triggered asynchronously in the main. Its DMA transfer triggers an ISR at low priority at the end.

Sometimes, the DMA of the SDIO is enabled and the timer ISR is triggered at this time which enables the SPI DMA even if the SDIO DMA is already working.

But it's not a problem (at least during a while) because the DMA arbiter should manage the priority and give it to the SPI DMA (according to the reference manual and AN4031) and the data are well written for both SPI and SDIO.

But after a while (a random timing like few hundred milliseconds) the SPI DMA ISR doesn't trigger anymore and the SPI appears to be always busy in Rx Tx mode.

This issue always occurs after a case when the SDIO DMA stream is already enabled and the SPI DMA transfer is launched by the timer ISR.

I don't understand the reason why it's working during a while and then it stops.

Do I miss something ?

Thank you for your answer

This topic has been closed for replies.

3 replies

francois06
francois06Author
Associate II
April 26, 2019

I will clarify my question :

Is it possible to start a DMA2 transfer on the SPI1 which has a higher priority just after having started a DMA2 transfer on the SDIO without having an issue on the SPI ? Should I wait until the SDIO peripheral finishes its task before starting the SPI transfer ?

Thank you

S.Ma
S.Ma
Principal
April 26, 2019

Do you mean on the DMA stream/channel table you change the selection in the same column?

In this case you need surely to get an interrupt on DMA completion before changing.

For SPI, if it is master, SPI DMA Rx will be the one to wait for transfer complete. (Tx will end before, hence no IT for it)

There are I think some proper sequence to disable a DMA and reenable it. Reference manual has to be carefully read.

francois06
francois06Author
Associate II
April 26, 2019

Thanks for your answer.

No, I never use the same column :

  • SPI1_RX = stream0/channel3
  • SPI1_TX = stream2/channel2
  • SDIO_TX = stream3/channel4 (or stream6/channel4 I tried both)

And as you adviced, I'm always waiting for the Rx IT for the SPI DMA.

I noticed the Enable bit of the SPI1_RX DMA doesn't reset after the conflict.

If I reset it manually, then the SPI DMA IT occurs but the data is corrupted.

I probably can't start simultaneously two peripherals with same DMA but different stream ?

Maybe the DMA can't manage this type of request ?

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