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Khetag Goiaev
Khetag Goiaev
Associate II
April 14, 2019
Question

Double signal on PWM driven by DMA

  • April 14, 2019
  • 1 reply
  • 1305 views

Just trying to set PWM with DMA

Buffer which I try to use as duty cycle

uint16_t BUF_DMA[6] = {3, 4, 2, 7, 9, 1};

PWM is started by button

HAL_TIM_PWM_Start_DMA(&htim1,TIM_CHANNEL_4,(uint32_t*)&BUF_DMA, 6);

Output I get

0690X000008AUpHQAW.png

I can't understand why BUF_DMA[3] and BUF_DMA[5] are doubling and tripling.

This topic has been closed for replies.

1 reply

waclawek.jan
waclawek.jan
Super User
April 14, 2019

The timer period appears to be 10, and even if we don't know the SYSCLK-to-timer clock ratio, this is probably pretty close to duration of one DMA transfer cycle. Then if there is something increasing the transfer time - other DMA transfer in the same DMA unit, conflict on bus with other busmaster - the transfer might get delayed beyond the point where it is accepted by the timer for the next period (assuming preload is on on the given CCR register).

Read AN2548.

The PWM with the last value gets of course repeated infinitely, until you change the timer settings - you presumably did so in the interrupt, and the three repetitions are result of the interrupt latency.

JW

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