STM32F7: Can I use ADC conversions at highest speed (2.4Msps) with 216MHz clock?

Now that's interesting... there's even a cheap Nucleo board for it, so worth looking it. The main downside for me is that there seems to be only the HAL libraries for it, no LL library. I've seen a lot of bugs in HAL (in the past at least), and I find it massively confusing compared to using lower level register access

Also, CubeMX doesn't seem to be able to find a clock solution for 8MHz HSE input and 400MHz max speed (8MHz is what the Nucleo board uses). But by using this as a starting point, I managed to find something that seems to work https://visualgdb.com/tutorials/arm/stm32/stm32h7/. Yet another reason to dislike the HAL, I guess :)

The H7 is incredibly flexible, so it looks as if I can get everything I need: 36MHz ADC, 48MHz for the USB, and 400MHz clock for maximum math performance.

Very nice suggestion thanks! Since I need to buy a Nucleo board one way or another, might as well go this way (if I manage to get dragged into 2019 and accept the HAL, that is :)

Actually, according to STM32CubeMx there is a solution for 216MHz with 48MHz USB clock (PLLM=4, PLLN=216, PLLP=2, PLLQ=9).

It's the ADC that doesn't have a /3 prescaler, only 2 and 4 (obviously), so needs a 72MHz multiple

Yes, I understand all of that pretty well, thanks. I spent 3 days poring over every scrap of information for the F4, and doing all sort of tests, instrumented with an oscilloscope. That doesn't help me much, though

First of all, there's no way to generate a 36MHz clock from any combination of prescalers and divisors if you select a 216MHz clock on a Nucleo board with 8MHz crystal (it might be possible with different crystals, haven't tried all combinations, but I doubt it). The only way to get a 36MHz ADC clock is to use a core clock of 144MHz. Try selecting the Nucleo F467 board in CubeMX and see if you can get a 36MHz ADC clock on the ADC. ADCLK uses PCLK2, and can use a 2 or 4 divider (higher, too, but not relevant here) , so since PCLK2 is 108MHz with a 216 core clock, you can only use a 4 divider, resulting in a 27MHz clock at best, decreasing the maximum sample rate to 1.8Msps from 2.4Msps per second. There's no /3 prescaler that can be used to get to 36MHz from 108MHz. not with the F4 or F7 clock tree (can be done with the H7, as pointed out)

Also, since, as I explained in my original question, I need to use all 3 ADCs at once (I'm actually sampling 6 channels, two per ADC, using triple regular scan mode), so can't use the triple interleaved mode. My actual ADC conversion rate is half the maximum possible, since each ADC channel must convert 2 separate samples. So from a theoretical 1.2Msps for all 6 channels (half the max 2.4Msps) I drop to 900K samples per second

And I really need at least 12 bits to have any hope to get a decent cross correlation between signals at those speeds. So I'm back to square one even with the F7 (which is better than the F4 in the sense that I can get 27MHz ADC clock instead of 21MHz clock at the maximum processor speed of respectively 216 and 168)

Or do what I'm doing now, dynamically changing the core clock from 144MHz to 168MHz once the ADC conversion is finished, but that seems to mess up the USB libraries and decrease USB reliability

The H7 looks like a winner, on the other hand

• F4: max ADCCLK 36MHz at 144MHz, max core at 168MHz, but ADCCLK reduced dramatically to 21MHz; Max 2.4Msps per ADC at 12bit, 36MHz ADCCLK, dropping to 1.4Msps when running at 168MHz
• F7: max ADCCLK at 144MHz, max core at 216MHz with ADCCLK at 27MHz (not as much of a loss) Max 2.4Msps per ADC at 12bit, 36MHz ADCCLK, dropping to 1.8Msps per ADC when runining at 216MHz
• H7: Max ADCCLK 36MHz at max core of 400MHz, no compromise. Max 3.6Msps at 16 bit, 4.5Msps at 12 bit, for each ADC. The H7 is a beast, both for ADC and core. Please note that the F4 and F7 can sample at max ADC speed any of the exposed channels, the H7 has only 6 channels called high speed, the remaining can only do 1 Msps, no matter the resolution (16 or 12 or even 6 bits it's all 1Msps). Luckily I only need to convert 6 channels, so the H7 would be much, much faster. If someone needed, say, 12 channels (each ADC sampling 4 inputs), the timing and management of the conversion would be a lot more challenging with an H7 than an F4 or F7 (might still be faster in some cases)