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Amir1
Amir1
Associate III
March 4, 2019
Question

Advancing debug steps clock by clock

  • March 4, 2019
  • 5 replies
  • 957 views

Hello All

I understand that debug steps advance instruction by instruction (whether in C or assembly). I wonder if there is any way to advance CPU clock by CPU clock. I need this to debug an issue I have with the SysTick timer.

Thanks

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5 replies

waclawek.jan
waclawek.jan
Super User
March 5, 2019

Certainly not in some simple way accessible through a few clicks in an IDE.

> I need this to debug an issue I have with the SysTick timer.

Maybe you want to tell us about this issue, in a new thread.

JW

Amir1
Amir1Author
Associate III
March 5, 2019

Thanks. It would be nice to have that capability.

The issue is resolved. I was trying to use one of the SysTick timer bits to toggle a pin, and the intended frequency was too high given that I was using an if loop to set the gpio register. I wrongly attributed the lousy waveform to the timer. Nonetheless, it would be very nice if one could advance the debugger clock by clock sometimes.

Since we are here I should ask you this. Is that possible in STM32 to assign a particular bit of a variable to a particular bit of the ODR (I guess that is called atomic access in embedded programming lingo)? If the answer is yes, then my "if" loop becomes moot as I would be able to directly assign the desired timer bit (which I can extract by a simple mask) to the desired ODR bit.

Tesla DeLorean
Tesla DeLorean
Guru
March 5, 2019

There is bit-banding, but it is not good for peripherals because the smoke-n-mirrors to implement it aren't actually atomic. Same as doing RMW on TIM->SR there is a pretty large window to induce a hazard.

The GPIO has a 32-bit wide BSRR register which allows an bits within the 16-bit GPIO Bank to be set High or Low atomically without disturbing other bits/pins.

The CPU is static, I guess you could pulse the clock input one edge at a time if you really wanted too. But, in all honestly the silicon isn't going to implement a whole lot of magic debug functionality, for the ppb cases. The ITM/DWT/ETM stuff should cover most bases. But a whole lot of other pieces are clocking along autonomously from the processor. Get a trace pod for deeper analysis, and how-did-I-get-here problems. Usually cheaper just to instrument your code to understand flow and dynamic behaviour.

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waclawek.jan
waclawek.jan
Super User
March 5, 2019

> The CPU is static

Are you *sure*, Clive?

And how's the fabric around?

I was about to write the same in the morning, but then thought otherwise and had a look at the HSE-bypass specification in 'F407 datasheet. And guess what, it has a lower bound.

Yes I know it may be only the limitation of the semi-analog HSE cell, but...

Jan

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