STM32F071C PLL never gets ready on some boards

Question

I have a problem on a STM32F071C board. The PLL will not reach ready state. I am using the HSI and in order to reduce current consumption I want to devide PLL from 8MHz down to 2MHz. This works fine on most board (18 out of 20) but on some the PLL_RDY is never set. Do I violate any requirements by using RCC->CFGR2 = RCC_CFGR2_PREDIV_DIV4?

/* Enable Prefetch Buffer and set Flash Latency */

FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;

/* HCLK = SYSCLK */

RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;

/* PCLK = HCLK */

RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;

/* PLL configuration = HSI * 2 = 4 MHz */

RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL));

RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_PREDIV | RCC_CFGR_PLLMUL2);

RCC->CFGR2 = RCC_CFGR2_PREDIV_DIV4;

/* Enable PLL */

RCC->CR |= RCC_CR_PLLON;

/* Wait till PLL is ready */

while((RCC->CR & RCC_CR_PLLRDY) == 0)

{

}

/* Select PLL as system clock source */

RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));

RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;

/* Wait till PLL is used as system clock source */

while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)

{

}

Danish1 · Accepted Answer

As a comment, I don't like the way you modify RCC->CFGR, doing it in two hits with the first to clear some bits and the second to set others.

Looking at the data sheet section 6.3.9, I think the PLL should be able to sing between 16 and 48 MHz. So maybe getting the PLL to run at 8 MHz is outside the specification, and you have to run it at 16 MHz and divide by 2 (or whatever you want) to get HCLK.

Hope this helps,

Danish

Handzic.Dirk · Answer

You are right, I only checked the PLL input frequency which is ok down to 1 MHz but the min output frequency is 16 MHz. That is probably the problem.Thanks!

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