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Goguey.Pascal
Goguey.Pascal
Associate
January 9, 2019
Question

(many) DMAs to GPIO

  • January 9, 2019
  • 5 replies
  • 1260 views

Hello!

I have to build a system that throws data simultaneously to 6 16-bit ports. It should be bit-accurate, so I was thinking about preparing all the DMA channels with one single timer, and when everything is ready, start the timer. I already did that with the 2 DACs to get exact quadrature sine and cos waves and it works fine.

The purpose is to throw data into 3 Maxim DACs (6 channels) and clock them simultaneously.

I will probably use a H7, 208 pin package that has at least 6 full ports.

  1. Does it seem possible to make the same thing over 6 different ports?
  2. Does it seem possible to generate a clock that would clock the data in all the DACs simultaneously?

Thanks,

Pascal

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5 replies

AvaTar
AvaTar
Senior III
January 9, 2019

I don't know your timing requirements, but I would consider external shift registers with parallel outputs, like the CMOS 4094. You could load it per SPI, and trigger all at once.

This would be easy to synchronize, easy on the MCU pin count, but come at a higher BOM cost and less throughput.

Goguey.Pascal
Goguey.PascalAuthor
Associate
January 9, 2019

Hello AvaTar!

Thanks for your reply. External shift register, you mean in order to use less ports? But in this case indeed, the throughput would drop. That's why I was thinking of doing everything in the chip with DMA. If all the buffers have the same size, I can use the same DMA interrupt to update the 6 data buffers and it would (I hope) work quite smoothly. So I would like to keep things simple, use a chip with a lot of ports, DMA into the ports and that's it. With generation of a clock for the DACs. So basically I want to know if this is possible (i.e. 6 DMA channels depending on a single timer).

By the way, the BOM doesn't matter. The MAXIM DACs are quite expensive but I need some signal

quality and I have no choice here.

Thanks,

Pascal

AvaTar
AvaTar
Senior III
January 9, 2019

> But in this case indeed, the throughput would drop.

You would need to check with your performance requirements, SPI can achieve rates of several MByte/sec. The second advantage, you could sync the outputs of all shift registers at once, with a single output (assuming shift registers with latch/OE input).

> The MAXIM DACs are quite expensive but I need some signal quality and I have no choice here.

Remember I had been working with DACs from LT, with daisy-chainable serial inputs. Perhaps similar devices would be an opion for you.

> So I would like to keep things simple, use a chip with a lot of ports, DMA into the ports and that's it. With generation of a clock for the DACs. So basically I want to know if this is possible (i.e. 6 DMA channels depending on a single timer).

I didn't work much with concurrent DMA streams, but I see potential problems here.

First, you need to free all pins of a specific port, which will probably collide with other peripheral requirements.

Second, ST's GPIO ports use to be max. 16 bit wide (don't know the H7 here). And multiple DMA streams to different ports would have to share the peripheral bus, and thus still run sequentially. The output will then never by in sync.

But others here have more experience with such use cases.

S.Ma
S.Ma
Principal
January 9, 2019

16 or 32 bit write per cycle best case as the data bus is probably 32 bit for data and 16 bit for peripherals.

Max throughput probably would be to manage to map your DACs as memory interface.

Inspire yourself from LCD parallel interface 8080/6800 or parallel interface memory.

With this, and single memory interface, that would probably be the max throughput

For sure you'll still need some bus cycles to read the code in the flash... so expect some jitter minimized with max frequency.

FMC type peripheral with memory addressing by DMA.

waclawek.jan
waclawek.jan
Super User
January 10, 2019

Your description is not clear but I understand it so that you have several parallel-input DACs and you want to change their output regularly, simultaneously, and fast. It would help if you would post more details on the requirements.

DMA is no magic and data won't appear on several ports simultaneously. Also, there will be jitter in their timing depending on many factors (and even more factors in the overly complex H7), as KIC already pointed out.

Do the DACs latch data?

If yes, connect their trigger input together and drive it from a timer, which would also drive the DMA outputting the data so that they are all ready at the moment of triggering.

If no, and you need regularly changing output, consider adding latches externally.

JW

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