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Joerg Wagner
Joerg Wagner
Senior III
December 21, 2018
Solved

Want to store data in SRAM D2 domain, what is missing to avoid Hard fault?

  • December 21, 2018
  • 4 replies
  • 4608 views

Instead of using DTCMRAM or SRAM D1 domain via AXI, I set up the linker file to use D2.

In system_stm32h7xx.c I added the lines:

 /* Change the switch matrix read issuing capability to 1 for the AXI D2 target (Target 2 and INI2) */
 *((__IO uint32_t*)0x51003108) = 0x00000001;
 *((__IO uint32_t*)0x51043108) = 0x00000001;

But executing

/* Call static constructors */
 bl __libc_init_array

in startup_stm32h743xx.s a Hard Fault is thrown.

What is missing to have normal data stored in D2 domain?

Thank you for any tipps.

This topic has been closed for replies.
Best answer by Tesla DeLorean
Reset_Handler: 
 /* Enable D2SRAM clocks in RCC_AHB2ENR */
 ldr r0, =0x580244DC
 ldr r1, [r0]
 orr r1, #0xE0000000
 str r1, [r0]
...

4 replies

Tesla DeLorean
Tesla DeLorean
Guru
December 21, 2018

>>What is missing to have normal data stored in D2 domain? Thank you for any tips.

Enable the D2SRAM clocks? In SystemInit() prior to __libc_init_array call, or in startup.s

ie

 /* Enable D2 domain SRAM3 Clock (0x30040000 AXI)*/

 __HAL_RCC_D2SRAM3_CLK_ENABLE();

 /* Enable SRAM1/SRAM2/SRAM3 clocks on D2 domain */

 __HAL_RCC_D2SRAM1_CLK_ENABLE();

 __HAL_RCC_D2SRAM2_CLK_ENABLE();

 __HAL_RCC_D2SRAM3_CLK_ENABLE();

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Tesla DeLorean
Tesla DeLoreanBest answer
Guru
December 21, 2018
Reset_Handler: 
 /* Enable D2SRAM clocks in RCC_AHB2ENR */
 ldr r0, =0x580244DC
 ldr r1, [r0]
 orr r1, #0xE0000000
 str r1, [r0]
...

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Joerg Wagner
Joerg WagnerAuthor
Senior III
December 21, 2018

Great! Mastering the beast.

Any other places don't work, just in Reset_Handler only.

I spent too many hours with it, thank you.

Tesla DeLorean
Tesla DeLorean
Guru
December 21, 2018

If you get the Initial Stack Pointer set to unusable memory you're pretty much dead in the water. You can put a DTCMRAM address in the vector table, and subsequently load the SP with desired location/region

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Joerg Wagner
Joerg WagnerAuthor
Senior III
December 21, 2018

But I'm wondering about the necessity. Page 104 in RM0433 says:

Upon reset, clocks to blocks such as peripherals and some memories are disabled (except
for the SRAM, DTCM, ITCM and Flash memory).

And if I use D1 SRAM for data and work with Ethernet in D2, it works without enabling the clock for D2.

Tesla DeLorean
Tesla DeLorean
Guru
December 21, 2018

It is likely enabling some place else, I'd chase it down, but have more productive things to do.

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Singh.Harjit
Singh.Harjit
Senior
August 7, 2019

​I haven't seen this snippet of code before for the STM32H7 series part:

/* Change the switch matrix read issuing capability to 1 for the AXI D2 target (Target 2 and INI2) */

*((__IO uint32_t*)0x51003108) = 0x00000001;

*((__IO uint32_t*)0x51043108) = 0x00000001;

Can you share details around it? Is it for an errata item? Thanks.

HaiHuynh08
HaiHuynh08
Visitor II
July 15, 2021

It is in Table "AXI interconnect register map and reset values", Reference Manual. This table shows Offset of AXI_TARG2_FN_MOD (0x3108) and AXI_INI2_FN_MOD (0x43108). Because the base address of Global Programmer View (GPV) is 0x51000000 (as Table "Register boundary addresses"), so:

  • AXI_TARG2_FN_MOD at 0x51003108
  • AXI_INI2_FN_MOD at 0x51043108
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