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After Forever
After Forever
Senior III
December 19, 2018
Solved

STM32L431 errata - I2C "Spurious bus error detection in master mode"

  • December 19, 2018
  • 2 replies
  • 1303 views

ES0320 [1] describes an I2C errata "Spurious bus error detection in master mode":

Description

In master mode, a bus error can be detected spuriously, with the consequence of setting the BERR flag of the I2C_SR register and generating bus error interrupt if such interrupt is enabled. Detection of bus error has no effect on the I2C-bus transfer in master mode and any such transfer continues normally.

Workaround

If a bus error interrupt is generated in master mode, the BERR flag must be cleared by software. No other action is required and the ongoing transfer can be handled normally.

I have two questions:

  1. Does this mean we won't be able to detect actual bus error situations because we are required just to ignore it?
  2. Can a DMA transfer be halted because one of these "spurious" bus error detections? Or maybe we are in luck and DMA doesn't give any attention to the BERR flag?

Thank you.

[1] https://www.st.com/resource/en/errata_sheet/dm00218224.pdf

This topic has been closed for replies.
Best answer by Imen.D

Hello @After Forever​ ,

Unfortunately, it is true that we could miss real bus perturbations. I suppose that in case of a real error, the transfer would be stucked later on due to the clock counter desynchronization between master and slave, so a SW timeout would occur. But at IP level, we are not able to differentiate the true error from this spurious false error.

At silicon level, the DMA is not impacted by these errors. This flag is just an information with no hardware impact in master mode (on the contrary there are HW impacts in slave mode).

Best Regards,

Imen.

2 replies

After Forever
After ForeverAuthor
Senior III
January 8, 2019

Up

Imen.DBest answer
ST Technical Moderator
January 22, 2019

Hello @After Forever​ ,

Unfortunately, it is true that we could miss real bus perturbations. I suppose that in case of a real error, the transfer would be stucked later on due to the clock counter desynchronization between master and slave, so a SW timeout would occur. But at IP level, we are not able to differentiate the true error from this spurious false error.

At silicon level, the DMA is not impacted by these errors. This flag is just an information with no hardware impact in master mode (on the contrary there are HW impacts in slave mode).

Best Regards,

Imen.

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