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Andreas Bolsch
Andreas Bolsch
Lead III
December 7, 2018
Solved

Possible wrong FLASH_ACR description in STM32G0 RM

  • December 7, 2018
  • 1 reply
  • 886 views

STM32G071RB: According to RM 3.7.1 reset value of FLASH_ACR is 0x00040600, verified on hardware. But the description of indiviual bits doesn't fit.

RM: Bit 11 ICRST, Bit 10 reserved (cleared), Bit 9 ICEN, Bit 8 PRFTEN, so cache enabled, prefetch disabled, reserved bit set???

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Best answer by Antoine Odonne

​Hello Andreas,

Thank you for your comment, the error is in documentation, bit 10 is set indeed, RM will be updated in order to change the description for "Reserved, must be kept at reset value".

In other series this bit is used to enable DATA cache, which is ON after reset, but on G0 there is no DATA cache. This bit must be kept at reset value consequently.

Best regards,

Antoine

1 reply

Antoine OdonneBest answer
ST Employee
December 10, 2018

​Hello Andreas,

Thank you for your comment, the error is in documentation, bit 10 is set indeed, RM will be updated in order to change the description for "Reserved, must be kept at reset value".

In other series this bit is used to enable DATA cache, which is ON after reset, but on G0 there is no DATA cache. This bit must be kept at reset value consequently.

Best regards,

Antoine

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