STM32F7 USB Host - OTG_HCFG & OTG_HFIR values for Isochronous data

Question

What values should OTG_HCFG & OTG_HFIR (and USBPHYC_TUNE for internal HS PHY on STM32F7x3xx) be set to for Isochronous data?

As I understand it Isochronous data should be allocated 1 to 3 'slots' per Start of Frame (SOF) in full speed mode and up to 1 to 3 'slots' per Start of Frame (SOF) in high speed mode (with the option to request data more slowly.

As far as I can tell, the default settings provide one 'slot' per 8 micro-frames (every 8 SOFs or 1 'slot' every millisecond) - see https://community.st.com/s/question/0D50X00009fDLnPSAW/should-isochronous-data-be-received-on-every-microframe for details of my investigations so far.

Is there a way to change this behaviour?

I have a device that can provide up to 20M bits per second and cannot get that rate (it peaks at 8M bits per second) with the default values.

I think registers OTG_HCFG (section 32.15.18 of RM0431) and OTG_HFIR (section 32.15.19 of RM0431) as set by USB_InitFSLSPClkSel() in stm32f7xx_ll_usb.c are the correct registers, but there could be others that affect this.

Or is this data rate only possible with an external PHY?

Piers Hawksley · Answer

I have also modified USB_HC_Init (in stm32f7xx_ll_usb.c) to set the multi-count field (USB_OTG_HCCHAR_MC) in the host channel characteristics register - OTG_HCCHARx (see 32.15.25 in RM0431 Rev 3 - the reference manual for the STM32F72xxx / 3xxx). This should set the number of periodic (Interrupt & Isochronous) transactions per (micro)frame. It does not appear to have any affect.

See https://community.st.com/s/question/0D50X00009fDLnPSAW/should-isochronous-data-be-received-on-every-microframe for more of an update and a possible solution

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