Question
STM32F4Discovery - I2S config
Posted on July 22, 2013 at 18:28
Hi all!
I'm new in forum. I wrote this config for I2S. Instead of MCLK=256*Fs=12, 288000 MHz and CK=48KHz*32bit*2channel=3, 072000 MHz, I measured MCLK=4MHz and CK=1 MHz. My code is:RCC_APB1PeriphClockCmd (RCC_APB1Periph_SPI2, ENABLE);
// ..................../* Connect pins to I2S peripheral */
GPIO_PinAFConfig (PCM1804_PORTC, PCM1804_SCKI_PS, GPIO_AF_SPI2); // I2S2_SCKI GPIO_PinAFConfig (PCM1804_PORTB, PCM1804_I2S2_CK_PS, GPIO_AF_SPI2); // I2S2_CK GPIO_PinAFConfig (PCM1804_PORTB, PCM1804_I2S2_SD_PS, GPIO_AF_SPI2); // I2S2_SD GPIO_PinAFConfig (PCM1804_PORTB, PCM1804_I2S2_LRCK_PS, GPIO_AF_SPI2); // I2S2_LRCK , WS // I2S2 peripheral configuration I2S_InitTypeDef I2S2_InitStructure; SPI_I2S_DeInit (SPI2); /* For this standard, the WS signal is used to indicate which channel is being transmitted. It is activated one CK clock cycle before the first bit (MSB) is available. */ I2S2_InitStructure.I2S_Standard = I2S_Standard_Phillips; I2S2_InitStructure.I2S_DataFormat = I2S_DataFormat_24b; I2S2_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Enable; I2S2_InitStructure.I2S_AudioFreq = I2S_AudioFreq_48k; // I2S2_InitStructure.I2S_CPOL = I2S_CPOL_Low; // I2S2_InitStructure.I2S_Mode = I2S_Mode_MasterRx; // I2S_Init (SPI2, &I2S2_InitStructure); /* I2S_INTERRUPT */ NVIC_InitTypeDef NVIC_InitStructure; NVIC_InitStructure.NVIC_IRQChannel = SPI2_IRQn; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init (&NVIC_InitStructure); /* Enable the Rx buffer not empty interrupt */ SPI_I2S_ITConfig (SPI2, SPI_I2S_IT_RXNE, ENABLE); // I2S clock configuration in system file is:/************************* PLL Parameters *************************************/
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
#define PLL_M (uint32_t)8
#define PLL_N (uint32_t)336
/* SYSCLK = PLL_VCO / PLL_P */
#define PLL_P (uint32_t)2
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
#define PLL_Q (uint32_t)7
/* PLLI2S_VCO = (HSE_VALUE Or HSI_VALUE / PLL_M) * PLLI2S_N
I2SCLK = PLLI2S_VCO / PLLI2S_R */
#define PLLI2S_N (uint32_t)258
#define PLLI2S_R (uint32_t)3
/******************************************************************************/
/* I2S clock configuration */
/******************************************************************************/
/* PLLI2S clock used as I2S clock source */
RCC->CFGR &= ~RCC_CFGR_I2SSRC;
/* Configure PLLI2S */
RCC->PLLI2SCFGR = (PLLI2S_N << 6) | (PLLI2S_R << 28);
/* Enable PLLI2S */
RCC->CR |= ((uint32_t)RCC_CR_PLLI2SON);
/* Wait till PLLI2S is ready */
while((RCC->CR & RCC_CR_PLLI2SRDY) == 0)
{
}
