problem with clocking the SDIO for STM32F2xx

Posted on August 02, 2013 at 19:18

I have the PORT board , with STM32F207ZG , I have written my own SD library , since i did not feel good using the built in library , ...... the library i wrote is working correctly as it should be , and i wrote n read from the card correctly , but I just have a problem with clocking .... this is the configurations i have in the main ()

{

uint32_t temp; 

    temp=0;

    RCC->CFGR=0x00000000;

    RCC->CFGR|=(uint32_t)(0x09<<4);//AHB Prescalar of 4

    //RCC->CFGR|=(0x06<<13); //APB2 prescalar (if i uncomment this line , card wont initialize) 

    //

    //

    temp|=(0x08<<24); //  PLL Division factor for SDIO (PLLQ) = 8

    temp|=0x08;         // Main Division Factor for PLL input (PLLM) = 8  

    temp|=(0xC0<<6); // Main PLL multiplication factor (PLLN) = 192

    temp|=(3<<16); // Main Division Factor for PLL output (PLLP) = 8

    RCC->PLLCFGR=temp;

    RCC->CR|=(1<<24);

    while(!(RCC->CR & (1<<25))); // Waiting for PLL output to be ready

    //RCC->CFGR|=(1<<1); // PLL is the system clock (if i uncomment this line , the card wont initialize , idk y )

    //

    //

.

.

.

}

and on the SD_CARD_INIT()

{

  SDIO->CLKCR=0x00000000;    

  SDIO->CLKCR|=120; // Clock division factor but it has no meaning as long as bypass is enabled

 SDIO->CLKCR|=(1<<10); //By_pass enabled (if i comment this line , it wont work)

  SDIO->CLKCR|=(1<<8); // Clock enabled

  SDIO->POWER=0x00000003;

  //

  //  Initialization Sequence

  //

..

..

}

so the problem now is that i can not use the 96 MHz for the core processor or the card will fail initialization , even if i make sure that the clock on the APB2 domain is less than 60 MHz as the manual says , ..... but the other interesting fact is that according to these configurations , the card initialization is done via 48 MHZ clock , rather than 400KHZ or less ???!!!!!!!!!

This is urgent guys , cuz i really started to doubt this chip .