Question
TIM10 LSI
Posted on March 24, 2014 at 15:39
I'm working with STM32L151, and I'm trying to set the LSI clock as Timer 10 source. I tryed the following configuration but it didn't work properly (counts at system clock frequency). Can anyone help me to find the correct configuration?
Thank you!
// Enables LSI clock
RCC->CSR |= RCC_CSR_LSION;
// Waits LSI ready
while (!(RCC->CSR & RCC_CSR_LSIRDY)){__NOP();}
/* Enable TIM10 clocks */
RCC->APB2ENR|= RCC_APB2ENR_TIM10EN;
__DSB();
// Timer 10 Configuration
TIM10->CR1 = 0x0000; // tDTS = tCK_INT
// TIMx_ARR is not buffered
// Counter overflow and Setting the UG bit generate an UEV
// UEV enabled
// Counter disabled
TIM10->SMCR = 0x0000;
// ETR is non-inverted (Not used)
// External clock disable (counter is not clocked by edges on the ETRF)
// ETRP prescaler disabled
// ETRP not filtered
TIM10->SR = 0x0000; // Reset all Interrupt Flags
TIM10->DIER = TIM_DIER_UIE; // Capture Compare Interrupt DISABLED, Update Interrupt ENABLED
TIM10->CCER = 0x0000; // Ensure capture disabled (to modify TIM10->CCMR1 CC1S)
TIM10->CCMR1= TIM_CCMR1_CC1S_0;
TIM10->CCMR1= TIM_CCMR1_IC1F_0 | TIM_CCMR1_IC1PSC_1 | TIM_CCMR1_IC1PSC_0;
// Input mode:
// Sampling is done at fDTS
// Prescaler = 8
// CC1 channel is configured as input, IC1 is mapped on TI1
TIM10->CCER = TIM_CCER_CC1E; // Capture polarity non inverted/rising edge
// Capture enabled
TIM10->CNT = 0x0000; // Counter value
TIM10->PSC = 0x0000; // Prescaler = 1
TIM10->ARR = 0xFFFF; // Auto Reload Register
TIM10->CCR1 = 0x0000; // Compare Register
TIM10->OR = TIM_OR_TI1RMP_0; //Remap LSI to TIM10_CH1
// Initialize Interruption NVIC
NVIC_EnableIRQ(TIM10_IRQn);//Enable TIM10 Interruption
NVIC_SetPriority(TIM10_IRQn, NVIC_IPR0_PRI_0);//Priority 0
//Update Registers
TIM10->EGR = TIM_EGR_UG;
//TIM10 enable
TIM10->CR1 |= TIM_CR1_CEN;