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pawwodko
pawwodko
Associate II
June 10, 2014
Question

DMA into GPIO peripherial

  • June 10, 2014
  • 3 replies
  • 801 views
Posted on June 10, 2014 at 16:54

Hi all,

I have a project where I need to deal with 4-to-8 bit and 8-to-4 bit conversion and so I have a questions:

1. I know that I can do DMA to/from GPIO but what is maximum speed of that operation. Can I go up to 25 or 12.5 mega transactions per sec in any of the low end uC?

2. 8-to-4 bit coding requires D latches with OE, but if I could do the DMA transaction at 25MT/s into GPIO->MODE to set 4 pins of GPIO port into outputs and 4 into inputs and opposite I could do this 8-to-4 bit conversion without external latch. Is this possible using STM32?

Thank you for any help :)

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    3 replies

    Tesla DeLorean
    Tesla DeLorean
    Guru
    June 10, 2014
    Posted on June 10, 2014 at 19:00

    Here in the real world, we would use logic gates (PLD, FPGA, etc) to implement translations at these sorts of speed. You could use a PROM, EPROM, or FLASH type memory if the translation defies simple random logic. ie input data pattern via the address pins, output via the data pins

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    pawwodko
    pawwodkoAuthor
    Associate II
    June 10, 2014
    Posted on June 10, 2014 at 19:49

    clive1: Yes, I know that and I would prefer that solution but I must cut down unit price of final device and additional IC of 2-3$ is not acceptable.

    Major task is simple:  concatenate 2x4bit into one byte and transfer it to RAM and vice versa. At the end I will use additional D-type latches but it will cost $(not too much) and PCB area.

    But before that I must ask if this could be done by peripherals already present in IC.

    Tesla DeLorean
    Tesla DeLorean
    Guru
    June 10, 2014
    Posted on June 10, 2014 at 22:26

    So lets say we have an STM32F4 running at 168 MHz, several millions gates, and would have a budget of 6.72 machine cycles processing input data at 25 MHz

    If you sat in a tight loop who's only job was to read one block of GPIO bits, do a table translation, and output to another block of GPIO bits, I suspect one could probably do it at 25 MHz, and nothing else.

    As described the process might take a few 100 or 1000 logic gates.

    The SDIO port as 4-bits, and can clock at 25 MHz
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