Skip to main content
michael2399
michael2399
Associate II
August 15, 2017
Question

Preload for output compare for timer 1 - STM32F746

  • August 15, 2017
  • 1 reply
  • 3564 views
Posted on August 15, 2017 at 11:09

Hello,

I have a question to the note in the datasheet (RM0385 Rev 6, Page 682). Bit 3 OC1PE - Note 2.

What means this note?

'The PWM mode can be used without validating the preload register only in one

pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.'

We can use the preload only in one pulse mode. Is this correct? How can I validate the preload register?

Best regards,

Michael

    This topic has been closed for replies.

    1 reply

    waclawek.jan
    waclawek.jan
    Super User
    August 15, 2017
    Posted on August 15, 2017 at 13:11

    If you set that bit, the respective compare register (CCR1) does not get set immediately when you write it - the written value remains in an intermediate 'preload' register and it gets copied into the 'active compare register' at update event, i.e. when the counter (CNT) overflows (in upcounting mode). This is to prevent a missed pulse when you change CCR during counting (in PWM mode, compare output changes only at the moment of match).

    The above sentence is a cumbersome way to say exactly this.

    JW

      Terms & ConditionsAccessibility statement