system clock configuration issue in stm32f407vg

Posted on May 25, 2015 at 08:13

Chose a different multiplier, e.g. 2.

JW

Posted on May 25, 2015 at 11:52

PLLP (OK it's a divider rather than multiplier)

So if your PLL input clock is 2MHz, chose multiplier PLLN=168 thus PLL output is 2x168=336MHz and divider P=2 and your PLL output clock is then 168MHz.

The text in the RM under ''Caution'' may be misleading, PLLN is not restricted to 192..432, it's just the values which are allowed with 1MHz PLL input frequency.

JW

Posted on May 25, 2015 at 14:07

The text in the RM under ''Caution'' may be misleading, PLLN is not restricted to 192..432, it's just the values which are allowed with 1MHz PLL input frequency.

 

Thanks, how did you know that?Is it right for PLLI2SN too?

Posted on May 25, 2015 at 14:51

I'll try to get somebody with more authority to answer this. Please be patient.

JW

Posted on May 25, 2015 at 16:00

Because counter chains are speed limited, the critical path in the propagation is going to break the counter somewhere above 432 MHz

The VCO is generating very rapid impulses (not 50/50 duty), it's most stable region is between 192-432 MHz. Depending on the transistor speeds of the process this may be extended, ST have validated this range over the process window and temperature, so best to stick with those. I'd expect the failure mode in the the feedback loop (division/comparison, charge pump) to result in the VCO oscillating/modulating in an undesirable fashion.

The impulse nature is why you have to divide the PLL output by two, so you get the 50/50 duty the processor needs.

Perhaps someone for ST can explain the limitations better.