Keil assembly for stm32f4

; .s built using FPU support, ie --cpu Cortex-M4.fp
; High-throughput block transfer using the FPU register set as a 128-byte
; buffer.
;
; This implementation exploits the IT Folding feature of the Cortex-M4.
; An IT instruction following a 16-bit Thumb instruction, when both are
; aligned into a 32-bit memory word, takes no additional cycles to issue.
;
; Arguments:
; r0 source address
; r1 destination address
; r2 number of words to transfer.
_Z10copy_wordsPKmPmm PROC
 EXPORT _Z10copy_wordsPKmPmm
 ; The caller may have been using floating point.
 ; Save the callee-save portion of the register file.
 vpush {s16 - s31} ; 17
 ; 'Warm up' the transfer engine, which wants to operate in units of
 ; 128 bytes, by making smaller transfers until count a multiple of 
 lsrs.n r2, #1 ; 1
 itt cs ; 0 (aligned)
 vldmcs.32 r0!, {s0} ; 2
 vstmcs.32 r1!, {s0} ; 2
 lsrs.n r2, #1 ; 1
 itt cs ; 0 (aligned)
 vldmcs.32 r0!, {s0 - s1} ; 1+1+1
 vstmcs.32 r1!, {s0 - s1} ; 1+1+1
 lsrs.n r2, #1 ; 1
 itt cs ; 0 (aligned)
 vldmcs.32 r0!, {s0 - s3} ; 1+1+3
 vstmcs.32 r1!, {s0 - s3} ; 1+1+3
 lsrs.n r2, #1 ; 1
 itt cs ; 0 (aligned)
 vldmcs.32 r0!, {s0 - s7} ; 1+1+7
 vstmcs.32 r1!, {s0 - s7} ; 1+1+7
 lsrs.n r2, #1 ; 1
 itt cs ; 0 (aligned)
 vldmcs.32 r0!, {s0 - s15} ; 1+1+15
 vstmcs.32 r1!, {s0 - s15} ; 1+1+15
 ; Handle the case where we've been asked to transfer <32 words.
 ; In such a case, count will now be zero, and the Z flag will still
 ; be set from the last XFER.
 ;
 ; Force the branch to use a 32-bit instruction to preserve alignment
 ; of the loop branch below; this saves a cycle per time that branch
 ; is taken.
 ;
 ; Note that the target of this branch (at 1 below) is also aligned,
 ; saving a cycle on the rare escape path.
 beq.n z1 ; 1 (n.t.)
 ; All warmed up, transfer in units of 128 bytes.
z0 vldm.32 r0!, {s0 - s31} ; 33
 vstm.32 r1!, {s0 - s31} ; 33
 subs.n r2, #1 ; 1
 bne.n z0 ; ~3 (taken)
 ; Restore FPU state.
z1 vpop {s16 - s31} ; 17
 bx lr ; 1-3??
 ENDP ; _Z10copy_wordsPKmPmm
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