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hbarta2
hbarta2
Associate III
December 12, 2016
Solved

STM32F746G-DISCO CubeMX Ethernet buglet

  • December 12, 2016
  • 6 replies
  • 1536 views
Posted on December 12, 2016 at 16:51

CubeMX version 4.18.0 sets the PHY Address Value for the on board PHY (LAN8742A) as 1. This does not work. It cannot even be changed in CubeMX without switching to 'user PHY'. 

In order for the on board Ethernet to work the user can go into stm32f7xx_hal_config.h and change the macro that defines LAN8742A_PHY_ADDRESS to 0.

#stm32cubemx-ethernet #stm32f7-discovery-kit
This topic has been closed for replies.
Best answer by stm32cube-t
Posted on January 02, 2017 at 15:48

Hello,

The Phy address name issue will be fixed in next 4.19 release. To change the Phy address value go to the Parameter Settings tab.

6 replies

Imen.D
ST Technical Moderator
December 13, 2016
Posted on December 13, 2016 at 18:24

Hello

Barta.Hank

‌,

I will report your issue internallyfor checking.

Thank you for highlighting this caseand Sorry for the inconvenience it may bring.

Best Regards

-Imen-

In order to give better visibility on the answered topics, please click on 'Best answer' on the reply which solved your issue or answered your question. Thanks
hbarta2
hbarta2Author
Associate III
December 14, 2016
Posted on December 14, 2016 at 20:02

Thank you. 

Another issue is that the Ethernet interrupt priority is left at 0 which does not work with FreeRTOS.

stm32cube-t
stm32cube-tBest answer
ST Employee
January 2, 2017
Posted on January 02, 2017 at 15:48

Hello,

The Phy address name issue will be fixed in next 4.19 release. To change the Phy address value go to the Parameter Settings tab.

Adalgiso
Adalgiso
Associate III
March 2, 2017
Posted on March 02, 2017 at 13:39

 ,

 ,

I do have the same issue with the code generated for the stm32F2 device.

Additionally some values are not correct, below is the value we should have (based on the demo for the nucleo 207 board).

/* Section 4: Extended PHY Registers */

 ,

♯ define PHY_SR ((uint16_t)0x1FU) /*!<, PHY status register Offset */

♯ define PHY_SPEED_STATUS ((uint16_t)0x0004U) /*!<, PHY Speed mask */

 ,

♯ define PHY_DUPLEX_STATUS ((uint16_t)0x0010U) /*!<, PHY Duplex mask */

♯ define PHY_ISFR ((uint16_t)0x001DU) /*!<, PHY Interrupt Source Flag register Offset */

 ,

♯ define PHY_ISFR_INT4 ((uint16_t)0x0010U) /*!<, PHY Link down interrupt */
Nesrine M_O
Nesrine M_O
Associate
March 6, 2017
Posted on March 06, 2017 at 16:44

refer to

https://community.st.com/0D50X00009XkiUKSAZ

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