Address cycle calculations for external flash.

Posted on May 17, 2011 at 12:52

I am trying to do the address cycle calculations for the external flash that i am driving with a STM32F103. The data sheet for the Micron flash chip has 5 address cycles for it. In one of the sample examples in FWLib, they have used a a 512Mb external memory which needs 4 address cycles to specify the the column page and block addresses. Here is how they have computed the calculations for it.

/* FSMC NAND memory address computation */

#define ADDR_1st_CYCLE(ADDR) (u8)((ADDR)& 0xFF) /* 1st addressing cycle */

#define ADDR_2nd_CYCLE(ADDR) (u8)(((ADDR)& 0xFF00) >> 8) /* 2nd addressing cycle */

#define ADDR_3rd_CYCLE(ADDR) (u8)(((ADDR)& 0xFF0000) >> 16) /* 3rd addressing cycle */

#define ADDR_4th_CYCLE(ADDR) (u8)(((ADDR)& 0xFF000000) >> 24) /* 4th addressing cycle */

If anyone has worked with this example before or any external flash memory can you please help me break this down?

The document is AN2784.

Thanks for your help.