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diverger
Senior
March 24, 2016
Question

FMC configuration bug in STM32CubeMX 4.14.0

  • March 24, 2016
  • 3 replies
  • 717 views
Posted on March 24, 2016 at 15:59

In STM32CubeMX 4.14.0, I find I can only set the address setup time, data setup time and bus turn around time for NOR/PSRAM timing. Other parameters like ''address hold time'', ''clock division'' and ''data latency'' are fixed to 15, 16 and 17 in the generated code. How CubeMX get these values? I wonder if it's designed to behave this?

My target chip are STM32F429/439IGTx.

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    3 replies

    slimen
    slimen
    Visitor II
    March 29, 2016
    Posted on March 29, 2016 at 18:48

    Hello diverger, 

    I have tested with different configurations and only the ''data latency'' value changed from 2 to 17.

    - 0000: Data latency of 2 CLK clock cycles for first burst access

    - 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)

    To have more idea about these parameters and configuration's, you can refer to the

    http://www2.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/_jcr_content/translations/en.DM00031020.pdf

    , exactly in (page 1629) section: SRAM/NOR-Flash chip-select timing registers 1..4 (FMC_BTR1..4)

    -ForumSTM32-

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    divergerAuthor
    Senior
    March 30, 2016
    Posted on March 30, 2016 at 05:57

    In my design, I configure the ''Memory type'' to ''SRAM'',  and in ''FMC Configuration'' wizard, under the section ''NOR/PSRAM timing'', only three item show, they are ''Address setup time'', ''Data setup time'', and ''Bus turn around time''. But in the source code, apparently we can change more parameters, such as the ''address  hold'' time, but why STM32CubeMX give *less* choice to us? Or the ''address hold'' time is not useful for ''SRAM''?

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    divergerAuthor
    Senior
    March 30, 2016
    Posted on March 30, 2016 at 06:27

    Thanks for your suggestions. After reading the datasheet carefully, I find it states at page 1569 (RM0090, rev. 11):

    Bits 7:4 ADDHLD[3:0]: Address-hold phase duration

    These bits are written by software to define the duration of the address hold phase (refer to Figure 443 to Figure 446), used in mode D and multiplexed accesses...

    So, I think this parameter is not cared when choose ''SRAM''.

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