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GreenGuy
GreenGuy
Senior III
May 16, 2018
Solved

AN4838 S field equivalent to non-cacheable

  • May 16, 2018
  • 1 reply
  • 886 views
Posted on May 17, 2018 at 00:50

In AN4838 it states on page 7/16:

The STM32F7 Series and

STM32H7 Series do not support hardware coherency. the S field is equivalent to non-cacheable memory.

Aside from the typo, I find this information to be confusing.  Does this mean that in F/H7 series devices that the S bit determines the cache behavior and is inter changeable with the C bit?  Or is it ignored?  Or is the S field and the S bit two different things?

Please clarify?

    This topic has been closed for replies.
    Best answer by Khouloud GARSI
    Posted on May 18, 2018 at 12:02

    Yes, correct.

    1 reply

    Khouloud GARSI
    Khouloud GARSI
    ST Employee
    May 17, 2018
    Posted on May 17, 2018 at 13:07

    Hello

    greenwood.greg

    ‌,

    The Shared attribute S is handled differently between Cortex-A and Cortex-M: In cortex-A, enabling S bit will enable Hardware coherency. However, cortex-Mdoesn’t support Hardware coherency snooping. So,enabling the S bit will automatically disable the cache.

    Khouloud.

    GreenGuy
    GreenGuyAuthor
    Senior III
    May 17, 2018
    Posted on May 17, 2018 at 18:20

    So then using a statement like:

    MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;

    will override:

    MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;

    in the same region making that region NOT cacheable.

    In the same vein:

    MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;

    MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;

    in the same region is redundant.

    Would that be correct?

    Khouloud GARSI
    Khouloud GARSIBest answer
    ST Employee
    May 18, 2018
    Posted on May 18, 2018 at 12:02

    Yes, correct.

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