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nikhilgopale
nikhilgopale
Associate
August 10, 2017
Question

STM32746G RTC problem

  • August 10, 2017
  • 10 replies
  • 2077 views
Posted on August 10, 2017 at 08:56

Hi Everyone,

I am working on RTC with stm32f746g controller. I tried number of option but i am not getting accurate time.

After some time rtc is getting lag of 4 to 5 seconds and it keep on lagging in time.

I am using 32.768khz exteranl crystal with 24pf capacitors.

I tried by changing this capacitors value 22pf,15pf,10pf also but still my problem is not solved.

I did internal rtc calibration also to minimize this error by changing prescaler values but still i am getting time lag.

Can anyone suggest me any other option which will work out and i will get accurate time?

    This topic has been closed for replies.

    10 replies

    waclawek.jan
    waclawek.jan
    Super User
    August 10, 2017
    Posted on August 10, 2017 at 13:28

    After some time rtc is getting lag of 4 to 5 seconds and it keep on lagging in time.

    After what time? When talking about error in measuring real-time, it's customary to give it in ppm = parts per million = (deviation / total elapsed time) * 1,000,000.

    With the LSE/32.768kHz crystal, up to 100ppm is relatively normal, 10ppm is what can be achieved with moderate effort. 100ppm converts into cca 8 seconds per day.

    JW

    nikhilgopale
    nikhilgopaleAuthor
    Associate
    August 10, 2017
    Posted on August 10, 2017 at 14:05

    Hi

    Waclawek.Jan

    ,

    In 12 hours i am getting almost 15 minutes time lag. As per formula

    (deviation / total elapsed time) * 1,000,000

    it is 20833 ppm.

    I am using AB38T-768KHZ crystal.

    waclawek.jan
    waclawek.jan
    Super User
    August 10, 2017
    Posted on August 10, 2017 at 14:36

    That's way too much.

    Read out and post the content of RCC_BDCR, RTC_PRER and RTC_CALR.

    JW

    nikhilgopale
    nikhilgopaleAuthor
    Associate
    August 11, 2017
    Posted on August 11, 2017 at 10:10

    In RCC_BDCR register LSE_ON & LSE_EN bit is set 

    i am using LSE as a clock source for RTC (RCC_RTCCLKSOURCE_LSE ).

    Configured RTC prescaler values so i should get 1 Hz frequency as mentioned below . 

    RTC_ASYNCH_PREDIV --> 0x7F 

    RTC_SYNCH_PREDIV --> 0x00FF 

    (mentioned in a  AN4759)

    I am using calender feature of rtc to get accurate time and date. 

    Tesla DeLorean
    Tesla DeLorean
    Guru
    August 10, 2017
    Posted on August 10, 2017 at 15:06

    Make sure the prescaler/divider values are correct. N-1

    There should be a way to benchmark LSE vs HSE or PLL, you should quantify the actual crystal speed, and use that to tweak the calibration, prescaler and divider values. Should also be possible emit LSE via a pin.

    Is the crystal in question a 6-7pF one, or a 9 or 12pF one? STM32 parts have historically worked far better with the former.

    Tips, Buy me a coffee, or three.. PayPal Venmo (See Profile) Up vote any posts that you find helpful, it shows what's working..
    nikhilgopale
    nikhilgopaleAuthor
    Associate
    August 11, 2017
    Posted on August 11, 2017 at 10:18

    Prescaler values are set correctly which is given below.

    RTC_ASYNCH_PREDIV --> 0x7F 

    RTC_SYNCH_PREDIV --> 0x00FF 

    It is mentioned in ST application note AN4759.

    I am using 32.768Khz crystal with load capacitance 12.5pF (digikey part no 

    535-9034-ND )

    waclawek.jan
    waclawek.jan
    Super User
    August 11, 2017
    Posted on August 11, 2017 at 18:29

    Read out and post the WHOLE content of RCC_BDCR, RTC_PRER and RTC_CALR.

    JW

    STOne-32
    STOne-32
    ST Technical Moderator
    August 11, 2017
    Posted on August 11, 2017 at 21:08

    Hi

    Gopale.Nikhil

    ‌,

    I checked your watch crystal pullability which is good from Abracon datasheet. The PPMs you have are not normal. ..

    I recommend you the following :

    1) Read our exaustive App note

    https://www.google.tn/url?sa=t&source=web&rct=j&url=http://www.st.com/resource/en/application_note/cd002216pdf&ved=0ahUKEwiFzuzw68_VAhVHQJoKHTaACFoQFggcMAE&usg=AFQjCNEN6KP-3BkBtlNX4u_tpDbFhRls6A

    Be patient to the end. I know it is long.

    2) First please in Firmware select our highest drive of LSE bits to 0x11 to be ableto match thus crystal :ESR max is 30KOhm which is helping a lot.

    3) CL1 =CL2 should be in range of 20pF . I Assumed your Cs =2.5pf bu I need your schematics and PCB layout to do a sanity check. You need to create a local ground loop to isolate PC14 and PC15 from other high speed signals crossing. .. I recommend then to do a tuning using an universal counter and output LSE clock at MCO pin PA8. Please do not use PC13 pin at thus step and avoid toggling it... it may disturb PC14 osc in.

    4) tune CL1 and CL2 until you will get a proper PA8 output at 768KHz +/- your PPMs. You can monitor your duty cycle also it should be in range if 40 to 60 %.

    5) Do not activate other peripherals. During (3). You can even put the CPU in sleep mode.

    6) I m sure you will untersrand and debug what is happening in your case.

    Cheers

    STOne -32

    nikhilgopale
    nikhilgopaleAuthor
    Associate
    August 12, 2017
    Posted on August 12, 2017 at 14:23

    Hi

    ,

    Please check attached schematic and layout of the board. Let me know hardware point of view it is correct or not.

    Also tell me how much Cs i should consider while calculating CL1 & CL2 values.Now i am using 24pf Capacitors.

    Nikhil

    ________________

    Attachments :

    layout.pdf : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HyW2&d=%2Fa%2F0X0000000b8s%2F9SOs0U4lN38YCBt8oaUjG64oYkbz70a_9ZqCQTjjwfg&asPdf=false

    schematic.pdf : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HyVs&d=%2Fa%2F0X0000000b8t%2FRuMyMU6VXiur6HoB.T2N9V2vdkW3cuIkcUDPz1f0joM&asPdf=false
    STOne-32
    STOne-32
    ST Technical Moderator
    August 13, 2017
    Posted on August 13, 2017 at 11:24

    Dear

    Gopale.Nikhil

    ‌,

    I would recommend you to monitor PA8 using an universal counter and see the LSE accuracy at 32,768KHz to find the right CL1 and CL1, the right value will have the closest frequency to Nominal.

    I strongly recommend to remove the 1MOhm parallel resistance and use its footprint to rework the watch crystal ( swapping its ends) as shown. It will increase the immunity of the osc-in versus the PC13 ( SD card ?).

    It may happen also due to PC13 and other high speed signals crossing some pulses are skipped and so the the huge drift. .. you can see iton PA8 also with an oscilloscope.

    I would recommend to start with CL1/ CL2 at 15 pF.

    0690X00000603vmQAA.jpg

    Cheers,

    STOne -32

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