DAC waveform not displaying on oscilloscope.

Posted on July 12, 2016 at 07:21

>   I'm doing a feedback of the adc output to the dac input to double check the incoming signal.

 

Most probably you mean the other way around - DAC output to ADC input.

>   However, when i put a oscilloscope probe to the DAC(PA5) the waveform shows, but then when i connect the osclloscope's gnd to the board's gnd, the signal flatlines and no waveform appears.

 

ST's DAC peripheral output stage is rather weak. Without buffer enabled, DAC output impedance is about 1 MOhm, and 15kOhm with buffer enabled. (This ''buffer'' is a configuration option of the DAC. Enabling it gives you up to 200mV offset at both rails ...).

This is definitely too weak to drive the ADC proper. However, you should at least see some waveform with the standard probe impedance of 10MOhm. If not, you probably missed something in the DAC initialisation.

Posted on July 12, 2016 at 16:54

Hi,

I can't really help you because I'm pretty inexperienced too, but if you actually want to generate a signal from the DAC to send it to the ADC there should be several examples doing this, especially in the standard libraries package for your device, and on this forum too (I'm using it myself).

From what I understand, you do the reverse, but if your examples are the same as mine (I have stm32f3xx), you have in the DAC examples folder a ''ADC-DAC loop'', in which you're supposed to send signal from DAC to ADC, and ADC to DAC. Just rearrange the first part (function generator to ADC and DAC to oscillo), and you should have a solid base for your project. I say that because your problem may come from bad configuration, so it could help, at least.

> This ''buffer'' is a configuration option of the DAC. Enabling it gives you up to 200mV offset at both rails ...

With rather high frequency (30 kHz), disabling the buffer gives me an ugly sine, not smooth, where I can see the samples. Any idea why?

Posted on July 13, 2016 at 07:53

> With rather high frequency (30 kHz), disabling the buffer gives me an ugly sine, not smooth, where I can see the samples. Any idea why?

 

If you refer to your thread regarding the unexpected low amplitude - I think clive is correct here. The slew rate of ST's DAC implementation is in the range from 2 us to 5 us.

Thus, going higher than 200kHz for the update frequency does not make much sense.

Additionally, you might review the buffer amplifier bandwidth in the specs.

Consider an external buffer amplifier, or an external DAC.

Posted on July 13, 2016 at 16:11

When you talk about going higher than 200 kHz for the update frequency, are you referring to this line:

Period = (SystemCoreClock / 960000); 

Where, having 32 samples, I aim for a sine frequency of 30 kHz? Are you saying instead of 960 kHz I should have a maximum of 333 kHz?

Because looking at the datasheet, tsettling is typically 3µs and max 4µs. So considering the frequency aspect, 1/0.000003 = 333 kHz, so ok. But 1/0.000004 = 250 kHz. With that, in order to not go higher than the max (4µs) in term of time, shouldn't it be considered as the minimum in term of frequency (so not lower than 250 kHz), and since the datasheet doesn't give any minimum time being virtually allowed to put any frequency above 250 kHz ?