STM32 timer input filter

Posted on August 26, 2016 at 17:55

Hi Hi zachai.arthur,,

The filtering stage is activated to reject clock signal pulses with duration shorter than a certain threshold.

T

he digital filter is made of an event counter in which Nconsecutive events are needed to validate a transition on the output. The ETF bit-fields (External trigger filter) defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP (see the “TIMx_SMCR� register in Reference manual for the available configurations).

Note that the maximal duration of filtered pulses depends on two parameters:

·

The configuration of the filtering stage respective to a certain timer input. For example, the ETR input filtering stage is configured through the ETF[3:0] control bit-field within the TIMx_SMCR register. The configuration of an input filtering stage implies the selection of a sampling clock source, the setting of the sampling clock frequency and the setting of the minimal time duration of a valid pulse in units of clock cycles of the already configured sampling clock.

• In the case that the FDTS clock source is used as sampling clock source, the filtering stage minimal valid pulse duration will be impacted by the by the value written to the CKD[1:0] control bit-field within the TIMx_CR1 register. The FDTS clock signal is derived from the timer clock signal, and the CKD[1:0] control bit-field sets the ratio between these two clock signals.

You can check the ''1.4.1 Filtering stage'' part of application note “General porpose Timers Cookbookâ€�

http://www.st.com/content/ccc/resource/technical/document/application_note/group0/91/01/84/3f/7c/67/41/3f/DM00236305/files/DM00236305.pdf/jcr:content/translations/en.DM00236305.pdf

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-Hannibal-