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edpeckham
edpeckham
Visitor II
October 27, 2016
Question

STM32F7(65) FMC NAND DCache issue

  • October 27, 2016
  • 2 replies
  • 751 views
Posted on October 27, 2016 at 14:52

I have a NAND flash connected to the FMC on my STM32F765VGT6 and using the HAL drivers (September 2016). I have noticed inconsistent behaviour when the DCache is enabled when polling the flash during HAL_NAND_Read_Status or reading the HAL_NAND_Read_ID.

Behaviours include:

* Bad data read back from the HAL_NAND_Read_ID

* Incorrect status values read from HAL_NAND_Read_Status

while prevent the flash from working.

When I disable the DCache, everything works fine.

The __DSB() calls are made after each IO read and write in the HAL drivers. I have tried also to clean the DCache after read and write operations, but the only working solution is to disable the DCache.

Has anybody got any suggestions to make this work with the DCache enabled? Let me know if you need more info.

Thanks,

Ed

#cortex-m7-cache
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    2 replies

    slimen
    slimen
    Visitor II
    October 27, 2016
    Posted on October 27, 2016 at 18:42

    Hello,

    Maybe this application note 

    http://www.st.com/en/embedded-software/x-cube-32f7perf.html

     about STM32F7 performance and the 

    http://www.st.com/content/ccc/resource/technical/document/application_note/group0/08/dd/25/9c/4d/83/43/12/DM00272913/files/DM00272913.pdf/jcr:content/translations/en.DM00272913.pdf

     can help you on this topic.

    Regards

    waclawek.jan
    waclawek.jan
    Super User
    October 27, 2016
    Posted on October 27, 2016 at 21:16

    Note that I am no expert and have nil experience with NAND together with the 'F7.

    > I have tried also to clean the DCache after read and write operations, but the only working solution is to disable the DCache.

    DSB ''only'' ensures that the processor's writes and reads complete before commending after DSB, but those writes may end in cache and reads may be from cache.

    If you want to break out of the cache without outright disabling it, you need to *invalidate* cache *before* read and *clean* *after* write.

    You can invalidate and clean not only the whole cache but also by addresses, which is maybe what you want. Look at ''Cache maintenance'' chapter in PM0253, namely DCIMVAC/DCCMVAC/DCCIMVAC.

    You can also disable cache for a portion of the address space - read the MMU-related chapters in the manuals, and above mentioned ANs.

    JW

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