Reset state for JTAG pins

Posted on May 17, 2011 at 13:17

Hi all,

I´ve seen on the reference manual in GPIO section that:

Quote:

The JTAG pins are in input PU/PD after reset:

PA15: JTDI in PU

PA14: JTCK in PD

PA13: JTMS in PU

PB4: JNTRST in PU

If I understand correctly, it´s that for example for PA15: MODE=00b(classic reset state input), CNF=10b (input pul-up/down) and ODR=1b(pull-UP)

Am I right?

But it´s not mentioned the reset state of PB3 (JTDO)...

I would like to write directly in this registers without read before like that:

GPIOB->CRL = vu32(GPIO_CRL_MODE0_0 + GPIO_CRL_CNF4_1 + GPIO_CRL_MODE5_1 + GPIO_CRL_MODE7_1); //only for example

But I want to use the JTAG and so not to disable it!

(I haven´t yet my board and so I can´t read the reset state of JTAGs pins)

Regards,

Vince

[ This message was edited by: lil-vince on 10-07-2009 17:24 ]